参数资料
型号: MAX16067ETJ+
厂商: Maxim Integrated Products
文件页数: 10/48页
文件大小: 0K
描述: IC SYSTEM MANAGER 6CH 32-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
应用: 电源监控器,序列发生器
电源电压: 2.8 V ~ 14 V
电流 - 电源: 2.8mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x5)
包装: 管件
6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
Detailed Description
The MAX16067 manages up to six system power sup-
plies. After boot-up, if EN is high and the software-enable
bit is set to ‘1,’ a power-up sequence begins based on
the configuration stored in flash and the EN_OUT_s are
controlled accordingly. When the power-up sequence is
successfully completed, the monitoring phase begins.
An internal multiplexer cycles through each MON_ input.
At each multiplexer stop, the 10-bit ADC converts the
monitored analog voltage to a digital result and stores
the result in a register. Each time a conversion cycle
(5 F s, max) completes, internal logic circuitry compares
the conversion results to the overvoltage and undervolt-
age thresholds stored in memory. When a result violates
a programmed threshold, the conversion can be con-
figured to generate a fault. GPIO_ can be programmed
to assert on combinations of faults. Additionally, faults
can be configured to shut off the system and trigger the
nonvolatile fault logger, which writes all fault information
automatically to the flash and write-protects the data to
prevent accidental erasure.
The MAX16067 contains both SMBus and JTAG serial
interfaces for accessing registers and flash. Use only
one interface at any given time. For more information
on how to access the internal memory through these
interfaces, see the SMBus-Compatible Serial Interface
and JTAG Serial Interface sections. The memory map
is divided into three pages with access controlled by
special SMBus and JTAG commands.
The factory-default values at POR (power-on reset) for all
RAM registers are ‘0’s. POR occurs when V CC reaches
the undervoltage-lockout threshold (UVLO) of 2.7V
(max). At POR, the device begins a boot-up sequence.
During the boot-up sequence, all monitored inputs are
masked from initiating faults and flash contents are
copied to the respective register locations. During boot-
up, the MAX16067 is not accessible through the serial
interface. The boot-up sequence takes up to 150 F s, after
which the device is ready for normal operation. RESET
is asserted low up to the boot-up phase after which it
assumes its programmed active state. RESET remains
active for its programmed timeout period once sequenc-
ing is completed and all monitored channels are within
their respective thresholds. Up to the boot-up phase, the
GPIO_s and EN_OUT_s are high impedance.
Power
Apply 2.8V to 14V to V CC to power the MAX16067.
Bypass V CC to ground with a 10 F F capacitor. Two inter-
nal voltage regulators, ABP and DBP, supply power to
the analog and digital circuitry within the device. For
operation at 3.6V or lower, disable the regulators by con-
necting ABP and DBP to V CC .
ABP is a 3.0V (typ) voltage regulator that powers the inter-
nal analog circuitry. Bypass ABP to GND with a 1 F F ceram-
ic capacitor installed as close as possible to the device.
DBP is an internal 3.0V (typ) voltage regulator. DBP
powers flash and digital circuitry. All push-pull outputs
refer to DBP. DBP supplies the input voltage to the inter-
nal charge pump when the programmable outputs are
configured as charge-pump outputs. Bypass the DBP
output to GND with a 1 F F ceramic capacitor installed as
close as possible to the device.
Do not power external circuitry from ABP or DBP.
Sequencing
To sequence a system of power supplies safely, the out-
put voltage of a power supply must be good before the
next power supply may turn on. Connect EN_OUT_ out-
puts to the enable input of the external power supplies
and connect MON_ inputs to the output of the power
supplies for voltage monitoring. More than one MON_
can be used if the power supply has multiple outputs.
Sequence Order
The MAX16067 provides a system of ordered slots to
sequence multiple power supplies. To determine the
sequence order, assign each EN_OUT_ to a slot ranging
from Slot 1 to Slot 6 (Table 6b). EN_OUT_(s) assigned to
Slot 1 are turned on first, followed by outputs assigned
to Slot 2 through Slot 6. Multiple EN_OUT_s assigned to
the same slot turn on at the same time.
Each slot includes a built-in configurable sequence
delay (registers r77h to r7Dh) ranging from 80 F s to
5.079s. During a reverse sequence, slots are turned off
in reverse order starting from Slot 6. The MAX16067 can
be configured to power down in simultaneous mode or
in reverse-sequence mode as set in r75h[0]. Set r75h[0]
to ‘1’ for reverse sequence power-down.
See Tables 5 and 6 for the MON_ and EN_OUT_ slot assign-
ment bits, and Tables 2 and 3 for the sequence delays.
During power-up or power-down sequencing, the cur-
rent sequencer state can be found in r21h[3:0].
10
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