参数资料
型号: MAX1639ESE+T
厂商: Maxim Integrated Products
文件页数: 11/13页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 16-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 电流模式
输出数: 1
频率 - 最大: 1.2MHz
占空比: 84%
电源电压: 4.5 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
High-Speed Step-Down Controller with
Synchronous Rectification for CPU Power
V OUT ( IN ( MAX ) ? V OUT )
L =
V
V IN ( MAX ) x f OSC x I OUT x LIR
In high-current applications, connect several resistors
in parallel as necessary to obtain the desired resis-
tance and power rating.
Selecting the Output Filter Capacitor
where f is the switching frequency, between 300kHz
and 1MHz; I OUT is the maximum DC load current; and
LIR is the ratio of AC to DC inductor current (typically
0.3). The exact inductor value is not critical and can be
adjusted to make trade-offs among size, transient
response, cost, and efficiency. Although lower inductor
values minimize size and cost, they also reduce efficien-
cy due to higher peak currents. In general, higher
inductor values increase efficiency, but at some point
resistive losses due to extra turns of wire exceed the
benefit gained from lower AC current levels. Load-
transient response can be adversely affected by
high inductor values, especially at low (V IN - V OUT )
differentials.
The peak inductor current at full load is 1.15 x I OUT if
the previous equation is used; otherwise, the peak cur-
rent can be calculated using the following equation:
Output filter capacitor values are generally determined
by effective series resistance (ESR) and voltage-rating
requirements, rather than by the actual capacitance
value required for loop stability. Due to the high switch-
ing currents and demanding regulation requirements in
a typical MAX1639 application, use only specialized
low-ESR capacitors intended for switching-
regulator applications, such as AVX TPS, Kemet T510,
Sprague 595D, Sanyo OS-CON, or Sanyo GX series. Do
not use standard aluminum-electrolytic capacitors,
which can cause high output ripple and instability due
to high ESR. The output voltage ripple is usually domi-
nated by the filter capacitor’s ESR, and can be approxi-
mated as I RIPPLE x R ESR . To ensure stability, the
capacitor must meet both minimum capacitance and
maximum ESR values as given in the following equa-
tions:
V OUT ?
I PEAK = I OUT +
V OUT ( V IN ( MAX ) ? V OUT
2 f OSC x L x V IN ( MAX )
)
C OUT >
?
V REF ? 1 + ?
? V IN ( MIN ) ?
V OUT x R SENSE x f OSC
The inductor’s DC resistance is a key parameter for effi-
cient performance, and should be less than the current-
sense resistor value.
Calculating the Current-Sense
Resistor Value
Calculate the current-sense resistor value according to
the worst-case minimum current-limit threshold voltage
(from the Electrical Characteristics ) and the peak
inductor current required to service the maximum load.
Use I PEAK from the equation in the section Specifying
the Inductor .
R ESR < R SENSE
Compensating the Feedback Loop
The feedback loop needs proper compensation to pre-
vent excessive output ripple and poor efficiency
caused by instability. Compensation cancels unwanted
poles and zeros in the DC-DC converter’s transfer func-
tion that are due to the power-switching and filter ele-
ments with corresponding zeros and poles in the
feedback network. These compensation zeros and
poles are set by the compensation components CC1,
R SENSE =
85 mV
I PEAK
CC2, and RC1. The objective of compensation is to
ensure stability by ensuring that the DC-DC converter’s
phase shift is less than 180° by a safe margin, at the
The high inductance of standard wire-wound resistors
can degrade performance. Low-inductance resistors,
such as surface-mount power metal-strip resistors, are
preferred. The current-sense resistor’s power rating
should be higher than the following:
I OUT ( MAX ) 2 x R SENSE
frequency where the loop gain falls below unity.
Canceling the Sampling Pole
and Output Filter ESR Zero
Compensate the fast-voltage feedback loop by con-
necting a resistor and a capacitor in series from the
CC1 pin to AGND. The pole from CC1 can be set to
cancel the zero from the filter-capacitor ESR. Thus the
capacitor at CC1 should be as follows:
______________________________________________________________________________________
11
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