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| 型号： | MAX1639ESE+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 9/13页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 16-SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.2MHz |
| 占空比： | 84% |
| 电源电压： | 4.5 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
High-Speed Step-Down Controller with
Synchronous Rectification for CPU Power
BST High-Side Gate-Driver Supply
and MOSFET Drivers
V IN = 5V
Gate-drive voltage for the high-side N-channel switch
is generated using a flying-capacitor boost circuit
BST
D2
C1
(Figure 3). The capacitor is alternately charged from
the +5V supply and placed in parallel with the high-
side MOSFET’s gate and source terminals.
LEVEL
TRANSLATOR
DH
LX
R4
N1
C3
Gate-drive resistors (R3 and R4) can often be useful to
reduce jitter in the switching waveforms by slowing
down the fast-slewing LX node and reducing ground
V DD
L1
bounce at the controller IC. However, switching loss
may increase. Low-value resistors from around 1 ? to
5 ? are sufficient for many applications.
CONTROL AND
DRIVE LOGIC
DL
PGND
R3
N2
Current Sense
and Overload Current Limiting
The current-sense circuit resets the main PWM latch
and turns off the high-side MOSFET switch whenever
the voltage difference between CSH and CSL from cur-
rent through the sense resistor (R1) exceeds the peak
current limit (100mV typical).
Current-mode control provides cycle-by-cycle current-
limit capability for maximum overload protection.
During normal operation, the peak current limit set by
the current-sense resistor determines the maximum
output current. When the output is shorted, the peak
current may be higher than the set current limit due to
delays in the current-sense comparator. Thus, foldback
current limiting is employed where the set current-limit
point is reduced from 100mV to 38mV as the output
(feedback) voltage falls (Figure 4). When the short-
circuit condition is removed, the feedback voltage will
MAX1639
Figure 3. Boost Supply for Gate Drivers
100
90
80
70
60
50
40
30
20
R3 AND R4
ARE OPTIONAL
rise and the current-limit voltage will revert to 100mV.
The foldback current-limit circuit is designed to ensure
startup into a resistive load.
High-Side Current Sensing
The common-mode input range of the current-sense
10
0
0 10 20 30 40 50 60 70 80 90 100
V FB (%)
inputs (CSH and CSL) extends to V CC , so it is possible
to configure the circuit with the current-sense resistor
on the input side rather than on the load side (Figure 5).
This configuration improves efficiency by reducing the
power dissipation in the sense resistor according to the
duty ratio.
In the high-side configuration, if the output is shorted
directly to GND through a low-resistance path, the
current-sense comparator may be unable to enforce a
current limit. Under such conditions, circuit parasitics
such as MOSFET R DS(ON) typically limit the short-
circuit current to a value around the peak-current-
limit setting.
Figure 4. Foldback Current Limit
Attach a lowpass-filter network between the current-
sense pins and resistor to reduce high-frequency
common-mode noise. The filter should be designed
with a time constant of around one-fifth of the on-time
(130ns at 600kHz, for example). Resistors in the 20 ? to
100 ? range are recommended for R9 and R10.
Connect the filter capacitors C9 and C10 from V CC to
CSH and CSL, respectively.
Values of 39 ? and 3.3nF are suitable for many
designs. Place the current-sense filter network close to
the IC, within 0.1 in (2.5mm) of the CSH and CSL pins.
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