MAX16826
Programmable, Four-String HB LED Driver with
Output-Voltage Optimization and Fault Detection
rising edge of the clock. When using external synchro-
nization, the clock frequency set by RTCT must be 10%
lower than the synchronization signal frequency.
Overvoltage Protection (OVP)
OVP limits the maximum voltage of the switching regu-
lator output for protection against overvoltage due to
circuit faults, for example a disconnected FB. Connect
OVP to the center of a resistor-divider connected
between the switching regulator output and GND to set
the output-voltage OVP limit. Typically, the OVP output
voltage limit is set higher than the load dump voltage.
Calculate the value of R15 and R16 as follows:
R15 = (V OVP /1.25 - 1) x R16
Or to calculate V OVP :
V OVP = 1.25 x (1 + R15/R16)
where R15 and R16 are shown in the Typical Application
Circuit. The internal OVP comparator compares the volt-
age at OVP with the internal reference (1.25V typ) to
decide if an overvoltage error occurs. If an overvoltage
error is detected, switching stops, the switching regula-
tor gate-drive output is latched off, and the soft-start
capacitor is discharged. The latch can only be reset by
toggling SYNC/EN, activating the I 2 C standby mode, or
cycling power.
The internal ADC also uses OVP to sense the switching
regulator output voltage. Output voltage measurement
information can be read back from the I 2 C interface.
Voltage is digitized to 7-bit resolution.
Undervoltage Lockout (UVLO)
When the voltage at V CC is below the V CC undervolt-
age threshold (V VCC_UVLO , typically 4.3V falling), the
MAX16826 enters undervoltage lockout. V CC UVLO
forces the linear regulators and the switching regulator
into shutdown mode until the V CC voltage is high
enough to allow the device to operate normally. In V CC
UVLO, the V CC regulator remains active.
Thermal Shutdown
The MAX16826 contains an internal temperature sensor
that turns off all outputs when the die temperature
exceeds +160°C. The outputs are enabled again when
the die temperature drops below +140°C. In thermal
shutdown, all internal circuitry is shut down with the
exception of the shunt regulator.
Linear Current Sources
(CS1–CS4, DL1–DL4)
The MAX16826 uses transconductance amplifiers to con-
trol each LED current sink. The amplifier outputs
(DL1–DL4) drive the gates of the external current sink FETs
Maxim Integrated
(Q2 to Q5 in the Typical Application Circuit). The source of
each MOSFET is connected to GND through a current-
sense resistor. CS1–CS4 are connected to the respective
inverting input of the amplifiers and also to the source of
the external current sink FETs where the LED string cur-
rent-sense resistors are connected. The noninverting input
of each amplifier is connected to the output of an internal
DAC. The DAC output is programmable using the I 2 C inter-
face to output between 97mV and 316mV. The regulated
string currents are set by the value of the current-sense
resistors (R28 to R31 in the Typical Application Circuit) and
the corresponding DAC output voltages.
LED PWM Dimming (DIM1–DIM4)
The MAX16826 features a versatile dimming scheme for
controlling the brightness of the four LED strings.
Independent LED string dimming is accomplished by dri-
ving the appropriate DIM1–DIM4 inputs with a PWM sig-
nal with a frequency up to 100kHz. Although the
brightness of the corresponding LED string is proportional
to the duty cycle of its respective PWM dimming signal,
finite LED current rise and fall times limit this linearity
when the dim pulse width approaches 2μs. Each LED
string can be independently controlled. Simultaneous
control of the PWM dimming and the LED string currents
in an analog way over a 3:1 range provides great flexibili-
ty allowing independent two-dimensional brightness con-
trol that can be used for color point setup and brightness
control.
Analog-to-Digital Converter (ADC)
The MAX16826 has an internal ADC that measures the
drain voltage of the external current sink driver FETs
(Q2 to Q5 in the Typical Application Circuit ) using
DR1 - DR4 and the switching regulator output voltage
using OVP. Fault monitoring and switching stage out-
put-voltage optimization is possible by using an exter-
nal microcontroller to read out these digitized voltages
through the I 2 C interface. The ADC is a 7-bit SAR (suc-
cessive-approximation register) topology. It sequential-
ly samples and converts the drain voltage of each
channel and V OVP . An internal 5-channel analog MUX
is used to select the channel the ADC is sampling.
Conversions are driven by an internally generated
1MHz clock and gated by the external dimming sig-
nals. After a conversion, each measurement is stored
into its respective register and can be accessed
through the I 2 C interface. The digital circuitry that con-
trols the analog MUX includes a 190ms timer. If the
ADC does not complete a conversion within this 190ms
measurement window then the analog MUX will
sequence to the next channel. For the ADC to complete
one full conversion, the cumulative PWM dimming on-
time must be greater than 10μs within the 190ms mea-
surement window. The minimum PWM dimming on-time
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