参数资料
型号: MAX17006BETP+T
厂商: Maxim Integrated Products
文件页数: 17/22页
文件大小: 0K
描述: IC BATT CHARGER 1.2MHZ 20-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
功能: 充电管理
电池化学: 多化学
电源电压: 8 V ~ 26 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-WFQFN 裸露焊盘
供应商设备封装: 20-TQFN-EP(4x4)
包装: 带卷 (TR)
1.2MHz, Low-Cost,
High-Performance Chargers
MOSFET Drivers
The DHI and DLO outputs are optimized for driving
moderate-sized power MOSFETs. The MOSFET drive
capability is the same for both the low-side and high-
sides switches. This is consistent with the variable duty
factor that occurs in the notebook computer environ-
ment where the battery voltage changes over a wide
turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold volt-
age, source inductance, and PCB layout characteris-
tics. The following switching-loss calculation provides
only a very rough estimate and is no substitute for
breadboard evaluation, preferably including a verifica-
tion using a thermocouple mounted on N1:
range. There must be a low-resistance, low-inductance
path from the DLO driver to the MOSFET gate to pre-
vent shoot-through. Otherwise, the sense circuitry in the
PD SW ( HS ) =
1
2
× t TRANS × V CSSP × I CHG × f SW
× ( Q GD + Q GS )
t TRANS = ?
+
V 2 CSSP × C RSS × f SW
PD CRSS ( HS ) ≈
MAX17005B/MAX17006B interpret the MOSFET gate as
off while there is still charge left on the gate. Use very
short, wide traces measuring 10 to 20 squares or fewer
(1.25mm to 2.5mm wide if the MOSFET is 25mm from
the device).
The high-side driver (DHI) swings from LX to 5V above
LX (BST) and has a typical impedance of 1.5 ? sourc-
ing and 0.8 ? sinking. The strong high-side MOSFET
driver eliminates most of the power dissipation due to
switching losses. The low-side driver (DLO) swings
from LDO to ground and has a typical impedance of 3 ?
sinking and 3 ? sourcing. This helps prevent DLO from
being pulled up when the high-side switch turns on due
to capacitive coupling from the drain to the gate of the
low-side MOSFET. This places some restrictions on the
MOSFETs that can be used. Using a low-side
MOSFET with smaller gate-to-drain capacitance can
prevent these problems.
Design Procedure
where t TRANS is the drivers transition time and can be
calculated as follows:
? 1 1 ?
?
? I GSRC I GSNK ?
I GSRC and I GSNK are the peak gate-drive source/sink
current (3 ? sourcing and 0.8 ? sinking, typically). The
MAX17005B/MAX17006B/MAX17015B control the
switching frequency as shown in the Typical Operating
Characteristics.
The following is the power dissipated due to high-side
n-channel MOSFET’s output capacitance (C RSS ):
2
The following high-side MOSFET’s loss is due to the
reverse-recovery charge of the low-side MOSFET ’s
body diode:
MOSFET Selection
Choose the n-channel MOSFETs according to the maxi-
mum required charge current. The MOSFETs must be
PD QRR ( HS ) =
Q RR2 × V CSSP × f SW
2
able to dissipate the resistive losses plus the switching
losses at both V DCIN(MIN) and V DCIN(MAX) .
For the high-side MOSFET, the worst-case resistive
power losses occur at the maximum battery voltage
and minimum supply voltage:
Ignore PD QRR (HS) if a Schottky diode is used parallel
to a low-side MOSFET.
The total high-side MOSFET power dissipation is:
PD TOTAL ( HS ) ≈ PD COND ( HS ) + PD SW ( HS )
PD COND ( HighSide ) =
V CSIN(MAX )
V DCIN ( MIN )
× I CHG 2 × R DS ( ON )
+ PD CRSS ( HS ) + PD QRR ( HS )
Switching losses in the high-side MOSFET can become
Generally, a low gate-charge high-side MOSFET is pre-
ferred to minimize switching losses. However, the
R DS(ON) required to stay within package power dissi-
pation often limits how small the MOSFET can be. The
optimum occurs when the switching losses equal the
conduction losses. High-side switching losses do not
usually become an issue until the input is greater than
an insidious heat problem when maximum AC adapter
voltages are applied. If the high-side MOSFET chosen
for adequate R DS(ON) at low-battery voltages becomes
hot when biased from V DCIN(MAX) , consider choosing
another MOSFET with lower parasitic capacitance.
For the low-side MOSFET (N2), the worst-case power
dissipation always occurs at maximum input voltage:
approximately 15V. Calculating the power dissipation in
N1 due to switching losses is difficult since it must
allow for difficult quantifying factors that influence the
?
PD COND ( LS ) = ? 1-
?
V CSIN ( MIN ) ? 2
? × I CH G × R DS ( ON )
V CSSP ( MAX ) ?
______________________________________________________________________________________
17
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