参数资料
型号: MAX17024ETD+T
厂商: Maxim Integrated Products
文件页数: 12/25页
文件大小: 0K
描述: IC REG CTRLR DIVIDER PWM 14TDFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: Quick-PWM™
PWM 型: 电流模式
输出数: 1
频率 - 最大: 600kHz
电源电压: 2 V ~ 26 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 85°C
封装/外壳: 14-WFDFN 裸露焊盘
包装: 带卷 (TR)
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
one-shot whose pulse width that is inversely proportion-
al to input voltage and directly proportional to output
voltage. Another one-shot sets a minimum off-time
(200ns typ). The on-time one-shot is triggered if the
error comparator is low, the low-side switch current is
below the valley current-limit threshold, and the mini-
mum off-time one-shot has timed out.
On-Time One-Shot
The heart of the PWM core is the one-shot that sets the
high-side switch on-time. This fast, low-jitter, adjustable
one-shot includes circuitry that varies the on-time in
response to input and output voltage. The high-side
switch on-time is inversely proportional to the input volt-
age as sensed by the TON input, and proportional to
the feedback voltage as sensed by the FB input:
On-Time (t ON ) = T SW (V FB / V IN )
where T SW (switching period) is set by the resistance
Power-Up Sequence (POR, UVLO)
The MAX17024 is enabled when EN is driven high, and
the 5V bias supply (V DD ) is present. The reference
powers up first. Once the reference exceeds its UVLO
threshold, the internal analog blocks are turned on and
masked by a 50μs one-shot delay to allow the bias cir-
cuitry and analog blocks enough time to settle to their
proper states. With the control circuitry reliably pow-
ered up, the PWM controller may begin switching.
Power-on reset (POR) occurs when V CC rises above
approximately 3V, resetting the fault latch and prepar-
ing the controller for operation. The V CC UVLO circuitry
inhibits switching until V CC rises above 4.25V. The con-
troller powers up the reference once the system
enables the controller, V CC exceeds 4.25V, and EN is
driven high. With the reference in regulation, the con-
troller ramps the output voltage to the target REFIN volt-
age with a 1.2mV/μs slew rate:
(R TON ) between TON and V IN . This algorithm results in
a nearly constant switching frequency despite the lack
of a fixed-frequency clock generator. Connect a resis-
t START =
V FB
1 . 2 mV / μ s
=
V FB
1 . 2 V / ms
T SW TON TON + 6 . 5 k ? ) ?
( R
? V FB ?
? V OUT ?
tor (R TON ) between TON and V IN to set the switching
period T SW = 1 / f SW :
= C ?
where C TON = 16.26pF. When used with unity-gain feed-
back (V OUT = V FB ), a 96.75k ? to 303.25k ? corresponds
to switching periods of 167ns (600kHz) to 500ns
(200kHz), respectively. High-frequency (600kHz) opera-
tion optimizes the application for the smallest compo-
nent size, trading off efficiency due to higher switching
losses. This may be acceptable in ultra-portable devices
where the load currents are lower and the controller is
powered from a lower voltage supply. Low-frequency
(200kHz) operation offers the best overall efficiency at
the expense of component size and board space.
For continuous conduction operation, the actual switching
frequency can be estimated by:
The soft-start circuitry does not use a variable current
limit, so full output current is available immediately.
PGOOD becomes high impedance approximately
200μs after the target REFIN voltage has been reached.
The MAX17024 automatically uses pulse-skipping mode
during soft-start and uses forced-PWM mode during
soft-shutdown.
For automatic startup, the battery voltage should be
present before V CC . If the controller attempts to bring
the output into regulation without the battery voltage
present, the fault latch trips. The controller remains shut
down until the fault latch is cleared by toggling EN or
cycling the V CC power supply below 0.5V.
If the V CC voltage drops below 4.25V, the controller
assumes that there is not enough supply voltage to
make valid decisions. To protect the output from over-
voltage faults, the controller shuts down immediately
and forces a high-impedance output (DL and DH
f SW =
V FB + V DIS
t ON ( V IN ? V CHG +V DIS )
pulled low).
Shutdown
where V DIS is the sum of the parasitic voltage drops in
the inductor discharge path, including synchronous recti-
fier, inductor, and PCB resistances; V CHG is the sum of
the resistances in the charging path, including the high-
When the system pulls EN low, the MAX17024 enters
low-power shutdown mode. PGOOD is pulled low
immediately, and the output voltage ramps down with a
1.2mV/μs slew rate:
=
side switch, inductor, and PCB resistances; and t ON is
the on-time calculated by the MAX17024.
t SHDN =
V FB V FB
1 . 2 mV / μ s 1 . 2 V / ms
12
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