参数资料
型号: MAX17024ETD+T
厂商: Maxim Integrated Products
文件页数: 15/25页
文件大小: 0K
描述: IC REG CTRLR DIVIDER PWM 14TDFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: Quick-PWM™
PWM 型: 电流模式
输出数: 1
频率 - 最大: 600kHz
电源电压: 2 V ~ 26 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 85°C
封装/外壳: 14-WFDFN 裸露焊盘
包装: 带卷 (TR)
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
Power-Good Outputs (PGOOD)
and Fault Protection
PGOOD is the open-drain output that continuously
monitors the output voltage for undervoltage and over-
voltage conditions. PGOOD is actively held low in shut-
down (EN = GND) during soft-start and soft-shutdown.
Approximately 200μs (typ) after the soft-start termi-
nates, PGOOD becomes high impedance as long as
the feedback voltage is above the PGOOD_L threshold
(REFIN - 200mV) and below the PGOOD_H threshold
(REFIN + 300mV). PGOOD goes low if the feedback
voltage drops 200mV below the target voltage (REFIN)
or rises 300mV above the target voltage (REFIN), or the
SMPS controller is shut down. For a logic-level PGOOD
output voltage, connect an external pullup resistor
between PGOOD and V DD . A 100k ? pullup resistor
works well in most applications. Figure 4 shows the
power-good and fault-protection circuitry.
PGOOD
When the feedback voltage drops 200mV below the
target voltage (REFIN), the controller immediately pulls
PGOOD low and triggers a 200μs one-shot timer. If the
feedback voltage remains below the V PGOOD_L thresh-
old for the entire 200μs, the undervoltage fault latch is
set and the SMPS begins the shutdown sequence.
When the internal target voltage drops below 0.1V, the
MAX17024 forces DL low. Toggle EN or cycle V CC
power below V CC POR to clear the fault latch and
restart the controller.
Thermal-Fault Protection (TSHDN)
The MAX17024 features a thermal fault-protection cir-
cuit. When the junction temperature rises above
+160°C, a thermal sensor activates the fault latch, pulls
PGOOD low, and shuts down the controller. Both DL
and DH are pulled low. Toggle EN or cycle V CC power
below V CC POR to reactivate the controller after the
junction temperature cools by 15°C.
MOSFET Gate Drivers
The DH and DL drivers are optimized for driving mode-
rate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in notebook applications, where a large V IN -
V OUT differential exists. The high-side gate driver (DH)
sources and sinks 1.5A, and the low-side gate driver
(DL) sources 1.0A and sinks 2.4A. This ensures robust
gate drive for high-current applications. The DH floating
high-side MOSFET driver is powered by internal boost
switch charge pumps at BST, while the DL synchro-
nous-rectifier driver is powered directly by the 5V bias
supply (V DD ).
Adaptive dead-time circuits monitor the DL and DH dri-
vers and prevent either FET from turning on until the
other is fully off. The adaptive driver dead time allows
operation without shoot-through with a wide range of
MOSFETs, minimizing delays and maintaining efficiency.
POWER-GOOD AND FAULT PROTECTION
TARGET
- 200mV
TARGET
+ 300mV
FB
EN
SOFT-START
COMPLETE
ONE-
SHOT
200 μ s
IN
OUT
V PGOOD_L
V PGOOD_H
UV FAULT
LATCH
UV FAULT
POWER-GOOD
CLK
Figure 4. Power-Good and Fault Protection
______________________________________________________________________________________
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