参数资料
型号: MAX17085GTL+
厂商: Maxim Integrated Products
文件页数: 16/38页
文件大小: 0K
描述: IC CHARGER/CTLR/LDO REG 40-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
功能: 充电管理
电池化学: 多化学
电源电压: 4.5 V ~ 24 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 托盘
Integrated Charger, Dual Main Step-Down
Controllers, and Dual LDO Regulators
Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
NAME
LX3
BST3
DL3
OUT3
LDO3
DCIN
LDO5
OUT5
DL5
BST5
LX5
DH5
DLC
BSTC
LXC
DHC
PGOOD
FUNCTION
Inductor Connection for SMPS3. Connect LX3 to the switched side of the inductor. LX3 is the lower
supply rail for the DH3 high-side gate driver.
Boost Flying Capacitor Connection for SMPS3. Connect to an external capacitor as shown in Figure
1. An optional resistor in series with BST3 allows the DH3 turn-on current to be adjusted. A 4.7ω
resistor is recommended to improve crosstalk between SMPSs.
Low-Side Gate-Driver Output for SMPS3. DL3 swings from PGND to LDO5.
Output Voltage-Sense Input for SMPS3. OUT3 is an input to the Quick-PWM on-time one-shot
timer. OUT3 also serves as the feedback input for the preset 3.3V, and the discharge path when in
shutdown. When OUT3 is in regulation, LDO3 is internally set to a lower level, and a bypass switch
between OUT3 and LDO3 is enabled.
3.3V Linear Regulator Output. LDO3 is the output of the 3.3V linear regulator supplied from LDO5.
LDO3 is switched over to OUT3 when SMPS3 is in regulation plus 200 F s. Bypass LDO3 to PGND with
a 4.7 F F or greater ceramic capacitor.
LDO5 Supply Input. Bypass DCIN with a 1 F F capacitor to PGND.
5V Linear Regulator Output. LDO5 provides the power to the MOSFET drivers. LDO5 is the output of the
5V linear regulator supplied from DCIN. LDO5 is switched over to OUT5 when SMPS5 is in regulation
plus 200 F s. Bypass LDO5 to PGND with a 4.7 F F or greater ceramic capacitor.
Output Voltage-Sense Input for SMPS5. OUT5 is an input to the Quick-PWM on-time one-shot timer.
OUT5 also serves as the feedback input for the preset 5V, and the discharge path when in shutdown.
When OUT5 is in regulation, LDO5 is internally set to a lower level, and a bypass switch between
OUT5 and LDO5 is enabled.
Low-Side Gate-Driver Output for SMPS5. DL5 swings from PGND to LDO5 .
Boost Flying Capacitor Connection for SMPS5. Connect to an external capacitor as shown in Figure
1. An optional resistor in series with BST5 allows the DH5 turn-on current to be adjusted. A 4.7ω
resistor is recommended to improve crosstalk between SMPSs.
Inductor Connection for SMPS5. Connect LX5 to the switched side of the inductor. LX5 is the lower
supply rail for the DH5 high-side gate driver.
High-Side Gate-Driver Output for SMPS5. DH5 swings from LX5 to BST5.
Low-Side Power MOSFET Driver Output for Charger. Connect to the low-side n-channel MOSFET
gate.
Boost Flying Capacitor Connection for Charger. Connect a 0.1 F F capacitor from BSTC to LXC, and a
Schottky diode from LDO5 to BSTC.
High-Side Driver Source Connection. Connect a 0.1 F F capacitor from BSTC to LXC.
High-Side Power MOSFET Driver Output for Charger. Connect to high-side n-channel MOSFET gate.
Open-Drain Power-Good Output for SMPS3 and SMPS5.
PGOOD is low when either SMPS3 or SMPS5 output voltage is more than 250mV (typ) below the
nominal regulation threshold, during soft-start, in shutdown (ON3 = ON5 = GND), and after either
fault latch has been tripped. After the soft-start circuit has terminated, PGOOD becomes high
impedance if the output is in regulation plus 200 F s.
When only one SMPS is active, PGOOD monitors the active SMPS output. When the 2nd SMPS is
started, PGOOD is blanked high-Z during the 2nd SMPS soft-start plus 200 F s, then PGOOD monitors
both SMPS outputs.
16
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