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参数资料
| 型号： | MAX17510ATB+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 11/13页 |
| 文件大小： | 0K |
| 描述： | IC REG DDR LOW VOLTAGE 10-TDFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 转换器，DDR |
| 输入电压： | 1.1 V ~ 3.6 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 1.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-WFDFN 裸露焊盘 |
| 供应商设备封装： | 10-TDFN-EP（3x3） |
| 包装： | 带卷 (TR) |
Low-Voltage DDR Linear Regulators
For a step voltage change at REFIN, the rate of change
of the output voltage is limited by the total output
SAFE OPERATING REGION
capacitance, the current limit, and the load during the
transition. Adding a capacitor across REFIN and AGND
filters noise and controls the rate of change of the
3.5
3.0
DROPOUT VOLTAGE
LIMITED
MAXIMUM CURRENT LIMIT
REFIN voltage during dynamic transitions. With the
additional capacitance, the REFIN voltage slews
between the two set points with a time constant given
by R EQ x C REFIN , where R EQ is the equivalent parallel
resistance seen by the slew capacitor.
2.5
2.0
1.5
T A = 0 ° C TO +70 ° C
V IN(MAX) - V OUT(MIN)
1s RMS
LIMIT
100s RMS
LIMIT
1.0
Operating Region and Power Dissipation
The maximum power dissipation of the MAX1510/
0.5
T A = +100 ° C
MAX17510 depends on the thermal resistance of the 10-
pin TDFN package and the circuit board, the tempera-
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
ture difference between the die and ambient air, and the
rate of airflow. The power dissipated in the device is:
P SRC = I SRC x (V IN – V OUT )
P SINK = I SINK x V OUT
The resulting maximum power dissipation is:
INPUT-OUTPUT DIFFERENTIAL VOLTAGE (V)
Figure 5. Power Operating Region—Maximum Output Current
vs. Input-Output Differential Voltage
V DROPOUT = R DS(ON) x I OUT
P DIS ( MAX ) =
T J(MAX ) - T A
θ JC + θ CA
For low output-voltage applications, the sink current is
limited by the output voltage and the R DS(ON) of the
MOSFET.
where T J(MAX) is the maximum junction temperature
(+150°C), T A is the ambient temperature, θ JC is the ther-
mal resistance from the die junction to the package case,
and θ CA is the thermal resistance from the case through
the PCB, copper traces, and other materials to the sur-
rounding air. For optimum power dissipation, use a large
ground plane with good thermal contact to the backside
pad, and use wide input and output traces.
When 1 square inch of copper is connected to the
device, the maximum allowable power dissipation of a
10-pin DFN package is 1951mW. The maximum power
dissipation is derated by 24.4mW/°C above T A = +70°C.
Extra copper on the PCB increases thermal mass and
reduces thermal resistance of the board. Refer to the
MAX1510 evaluation kit for a layout example.
The MAX1510/MAX17510 deliver up to 3A and oper-
ates with input voltages up to 3.6V, but not simultane-
ously. High output currents can only be achieved when
the input-output differential voltages are low (Figure 5).
Dropout Operation
A regulator’s minimum input-to-output voltage differen-
tial (dropout voltage) determines the lowest usable sup-
ply voltage. Because the MAX1510/MAX17510 use an
n-channel pass transistor, the dropout voltage is a func-
tion of the drain-to-source on-resistance (R DS(ON) =
0.25 Ω max) multiplied by the load current (see the
Typical Operating Characteristics):
Input Capacitor Selection
Bypass IN to PGND with a 10μF or greater ceramic
capacitor. Bypass V CC to AGND with a 1μF ceramic
capacitor for normal operation in most applications.
Typically, the LDO is powered from the output of a
step-down controller (memory supply) that has addi-
tional bulk capacitance (polymer or tantalum) and dis-
tributed ceramic capacitors.
Output Capacitor Selection
The MAX1510/MAX17510 output stability is indepen-
dent of the output capacitance for C OUT from 10μF to
220μF. Capacitor ESR between 2m Ω and 50m Ω is
needed to maintain stability. Within the recommended
capacitance and ESR limits, the output capacitor
should be chosen to provide good transient response:
Δ I OUT(P-P) x ESR = Δ V OUT(P-P)
where Δ I OUT(P-P) is the maximum peak-to-peak load-
current step (typically equal to the maximum source
load plus the maximum sink load), and Δ V OUT(P-P) is
the allowable peak-to-peak voltage tolerance.
Using larger output capacitance can improve efficiency
in applications where the source and sink currents
change rapidly. The capacitor acts as a reservoir for
the rapid source and sink currents, so no extra current
is supplied by the MAX1510/MAX17510 or discharged
to ground, improving efficiency.
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