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参数资料
| 型号： | MAX17535ETG+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 17/28页 |
| 文件大小： | 0K |
| 描述： | IC SMBUS BATT CHARGER 24TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 功能： | 充电管理 |
| 电池化学： | 锂离子（锂离子），多化学 |
| 电源电压： | 8 V ~ 26 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-WFQFN 裸露焊盘 |
| 供应商设备封装： | 24-TQFN-EP（4x4） |
| 包装： | 带卷 (TR) |
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High-Frequency,
Low-Cost SMBus Chargers
The data (SDA) and clock (SCL) pins have Schmitt-
trigger inputs that can accommodate slow edges.
Choose pullup resistors for SDA and SCL to achieve rise
times according to the SMBus specifications.
Communication starts when the master signals a START
condition, which is a high-to-low transition on SDA, while
SCL is high. When the master has finished communicating,
the master issues a STOP condition, which is a low-to-
high transition on SDA, while SCL is high. The bus is
then free for another transmission. Figures 4 and 5 show
the timing diagrams for signals on the SMBus interface.
a) Write-Word Format
The address byte, command byte, and data bytes are
transmitted between the START and STOP conditions.
The SDA state is allowed to change only while SCL is
low, except for the START and STOP conditions. Data
is transmitted in 8-bit bytes and is sampled on the rising
edge of SCL. Nine clock cycles are required to transfer
each byte in or out of the MAX17435/MAX17535 because
either the master or the slave acknowledges the receipt
of the correct byte during the ninth clock. The MAX17435/
MAX17535 support the charger commands as described
in Table 4.
S
SLAVE
ADDRESS
7 bits
MSB LSB
W
1b
0
ACK
1b
0
COMMAND
BYTE
8 bits
MSB LSB
ACK
1b
0
LOW DATA
BYTE
8 bits
MSB LSB
ACK
1b
0
HIGH DATA
BYTE
8 bits
MSB LSB
ACK P
1b
0
PRESET TO
Relearn() = 0x3D
D7
D0
D15
D8
0b0001001
ChargingCurrent() = 0x14
ChargerVoltage() = 0x15
b) Read-Word Format
S
SLAVE
ADDRESS
7 bits
MSB LSB
W
1b
0
ACK
1b
0
COMMAND
BYTE
8 bits
MSB LSB
ACK
1b
0
S
SLAVE
ADDRESS
7 bits
MSB LSB
R
1b
1
ACK
1b
0
LOW DATA
BYTE
8 bits
MSB LSB
ACK
1b
0
HIGH DATA
BYTE
8 bits
MSB LSB
NACK P
1b
1
PRESET TO
INP_Voltage() = 0x3E
PRESET TO
D7
D0
D15
D8
0b0001001
LEGEND:
S = START CONDITION OR REPEATED START CONDITION
ACK = ACKNOWLEDGE (LOGIC-LOW)
W = WRITE BIT (LOGIC-LOW)
MASTER TO SLAVE
SLAVE TO MASTER
Figure 3. SMBus Write-Word and Read-Word Protocols
0b0001001
P = STOP CONDITION
NACK = NOT ACKNOWLEDGE (LOGIC-HIGH)
R = READ BIT (LOGIC-HIGH)
A
t LOW
B
t HIGH
C
D
E
F
G
H
I
J
K
L
M
SMBCLK
SMBDATA
t SU:STA
t HD:STA
t SU:DAT
t HD:DAT
t HD:DAT
t SU:STO t BUF
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMBDATA LINE LOW
Figure 4. SMBus Write Timing
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE
H = LSB OF DATA CLOCKED INTO SLAVE
I = SLAVE PULLS SMBDATA LINE LOW
J = ACKNOWLEDGE CLOCKED INTO MASTER
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION, DATA EXECUTED BY SLAVE
M = NEW START CONDITION
______________________________________________________________________________________
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