参数资料
型号: MAX17535ETG+T
厂商: Maxim Integrated Products
文件页数: 25/28页
文件大小: 0K
描述: IC SMBUS BATT CHARGER 24TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
功能: 充电管理
电池化学: 锂离子(锂离子),多化学
电源电压: 8 V ~ 26 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-WFQFN 裸露焊盘
供应商设备封装: 24-TQFN-EP(4x4)
包装: 带卷 (TR)
High-Frequency,
Low-Cost SMBus Chargers
V DCIN(MAX) RSS SW LOAD
× C
× f
× I
? ? V BATT ? ? ? I LOAD ? 2
PD(Low - side) = ? 1- ? ? ? ? ? × R DS(ON)
? V BATT ?? I LOAD ?
PD(High - side) = ? ?? ? × R DS(ON)
Thehigh-sidedriver(DHI)swingsfromLXto5VaboveLX
(BST) and has a typical impedance of 1.5 I sourcing and
0.8 I sinking. The low-side driver (DLO) swings from DLOV
to ground and has a typical impedance of 3 I sinking and
3 I sourcing. This helps prevent DLO from being pulled
up when the high-side switch turns on due to capacitive
coupling from the drain to the gate of the low-side MOSFET.
This places some restrictions on the MOSFETs that can be
used. Using a low-side MOSFET with smaller gate-to-drain
capacitance can prevent these problems.
Design Procedure
MOSFET Selection
Choose the n-channel MOSFETs according to the maxi-
mum required charge current. Low-current applications
usually require less attention. The high-side MOSFET
(N1) must be able to dissipate the resistive losses plus
the switching losses at both V DCI(MIN) and V DCIN(MAX) .
Calculate both these sums.
Ideally, the losses at V DCIN(MIN) should be roughly equal
to losses at V DCIN(MAX) with lower losses in between. If
the losses at V DCIN(MIN) are significantly higher than the
losses at V DCIN(MAX) , consider increasing the size of N1.
Conversely, if the losses at V DCIN(MAX) are significantly
higher than the losses at V IN(MIN) , consider reducing the
size of N1. If DCIN does not vary over a wide range, the
minimum power dissipation occurs where the resistive
losses equal the switching losses. Choose a low-side
MOSFET that has the lowest possible on-resistance
(R DS(ON) ), comes in a moderate-sized package (i.e., one
or two 8-pin SO, DPAK, or D 2 PAK), and is reasonably
priced. Make sure that the DLO gate driver can supply
sufficient current to support the gate charge and the
current injected into the parasitic gate-to-drain capacitor
caused by the high-side MOSFET turning on; otherwise,
cross-conduction problems can occur. Select devices
that have short turn-off times, and make sure that:
N2(t DOFF(MAX) ) - N1(t DON(MIN) ) < 40ns, and
N1(t DOFF(MAX) ) - N2(t DON(MIN) ) < 40ns
Failure to do so could result in efficiency-reducing shoot-
through currents.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET, the worst-case
power dissipation (PD) due to resistance occurs at the
minimum supply voltage:
2
? V DCIN ? ? 2 ?
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages. However,
the R DS(ON) required to stay within package power-
dissipation limits often limits how small the MOSFET can
be. The optimum occurs when the switching (AC) losses
equal the conduction (R DS(ON) ) losses. Switching losses
in the high-side MOSFET can become an insidious
heat problem when maximum AC adapter voltages are
applied, due to the squared term in the CV 2 f switching-
loss equation. If the high-side MOSFET that was chosen
for adequate R DS(ON) at low supply voltages becomes
extraordinarily hot when subjected to V IN(MAX) , then
choose a MOSFET with lower losses. Calculating the
power dissipation in N1 due to switching losses is
difficult since it must allow for difficult quantifying factors
that influence the turn-on and turn-off times. These
factors include the internal gate resistance, gate charge,
threshold voltage, source inductance, and PCB layout
characteristics. The following switching-loss calculation
provides only a very rough estimate and is no substitute
for breadboard evaluation, preferably including a
verification using a thermocouple mounted on N1:
2
PD(HS_Switching) =
2 × I GATE
where C RSS is the reverse transfer capacitance of N1
and I GATE is the peak gate-drive source/sink current
(3.3A sourcing and 5A sinking).
For the low-side MOSFET (N2), the worst-case power
dissipation always occurs at maximum input voltage:
? ? V DCIN ? ? ? 2 ?
Inductor Selection
The charge current, ripple, and operating frequency
(off-time) determine the inductor characteristics. For
optimum efficiency, choose the inductance according to
the following equation:
L = V BATT O t OFF /(0.3 x I CHG )
This sets the ripple current to 1/3 the charge current and
results in a good balance between inductor size and
efficiency. Higher inductor values decrease the ripple
current. Smaller inductor values require high saturation
current capabilities and degrade efficiency.
Due to the minimum t OFF blanking effect upon zero-
crossing detection, higher inductor values are desired for
proper operation for a design with low input voltage and
high output voltage, especially for MAX17535.
______________________________________________________________________________________
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