参数资料
型号: MAX1802EHJ+
厂商: Maxim Integrated Products
文件页数: 19/28页
文件大小: 0K
描述: IC PWR SPLY STEP DOWN 32-TQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 360
应用: 控制器,数字式相机
输入电压: 2.5 V ~ 11 V
输出数: 5
输出电压: 1.25 V ~ 5.5 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-TQFP
供应商设备封装: 32-TQFP(5x5)
包装: 托盘
Digital Camera Step-Down
Power Supply
R OSC = (200ns - 1/f OSC ) / (C OSC + 10pF) ?
ln (1 - V REF / V VL )
See the Typical Operating Characteristics for f OSC vs.
R OSC using different values of C OSC . Due to duty cycle
limitation in the main controller, keep f OSC ≤ V MAIN /
(V VDDM(MAX) ? 500ns).
1.25
V OSC (V)
D MAX =
t H
t L + t H
Setting the Output Voltages
Set the MAX1802 output voltage of each converter by
connecting a resistive voltage-divider from the output
voltage to the corresponding FB_ input. The FB_ input
bias current is <100nA, so choose R L (the low-side
FB_-to-GND resistor) to be 100k ? . Choose R H (the
high-side output-to-FB_ resistor) according to the rela-
tion:
V DCON_
0.25
0
R H = R L ? OUT ? 1 ?
? ?
? V ?
1 . 248
CLK
t L
t H
Setting the Maximum Duty Cycle
The oscillator signal at OSC and the voltage at DCON_
are used to generate the internal clock signals for the
three MAX1802 auxiliary controllers (CLK in Figure 3).
The internal clock ’ s falling edge occurs when V OSC
exceeds V DCON _ (set by a resistive divider). The inter-
nal clock ’ s rising edge occurs when V OSC falls below
0.25V (Figure 5).
The adjustable maximum duty cycle range is 40% to
90% (see Maximum Duty Cycle vs. V DCON _ in the
Typical Operating Characteristics ). The maximum duty
cycle defaults to 76% at 100kHz if V DCON _ is at or
above the voltage at V REF (1.25V) (see Default
Maximum Duty Cycle vs. Frequency in the Typical
Operating Characteristics ). The controller shuts down if
V DCON _ is <0.3V.
Inductor Selection
Main and Core Step-Down Converters
Figure 5. Auxiliary Controller Internal Clock Signal Generation
In these equations, V DSP is the voltage drop across the
P-channel MOSFET switch, and V DSN is the voltage
drop across the N-channel MOSFET synchronous recti-
fier. Given L IDEAL , the consistent peak-to-peak inductor
current is 0.33 I OUT . The maximum inductor current is
1.17 I OUT .
Inductance values smaller than L IDEAL can be used;
however, the maximum inductor current will rise as L is
reduced, and a larger output capacitance will be
required to maintain the same output ripple. For stable
operation, the minimum inductance is limited by the
internal slope compensation. The minimum inductor
values for main and core are given by:
L MIN ( MAIN ) = ? 1 ?
MAX1802 main and core step-down converters offer
best efficiency when the inductor current is continuous.
For most designs, a reasonable inductor value (L IDEAL )
?
?
0 . 5 ? V OUT R DSP
D MAX ? ? 0 . 013 f OSC
? 3 ( V IN ? V DSP ) D ( 1 ? D ) ?
L IDEAL = ? ?
L MIN ( CORE ) = ? 1 ?
V OUT + V DSN
? V
+ V
can be derived from the following equation, which sets
continuous peak-to-peak inductor current at 1/3 the DC
inductor current:
? I OUT f OSC ?
where D, the duty cycle, is given by:
D =
V IN DSP DSN
and
? 0 . 5 ? V OUT
?
? D MAX ? 0 . 13 f OSC
where R DSP is the on-resistance of the P-channel MOS-
FET switch, and D MAX = V OUT / V IN .
Auxiliary Step-Up Controllers
The three MAX1802 auxiliary step-up controllers offer
best efficiency when the inductor current is continuous.
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