参数资料
型号: MAX1802EHJ+
厂商: Maxim Integrated Products
文件页数: 23/28页
文件大小: 0K
描述: IC PWR SPLY STEP DOWN 32-TQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 360
应用: 控制器,数字式相机
输入电压: 2.5 V ~ 11 V
输出数: 5
输出电压: 1.25 V ~ 5.5 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-TQFP
供应商设备封装: 32-TQFP(5x5)
包装: 托盘
Digital Camera Step-Down
Power Supply
To achieve a stable circuit for the core converter, use
the following procedure:
1) Determine the desired crossover frequency, either
1/3 of the zero due to the output capacitor ESR:
Discontinuous Inductor Current
For discontinuous inductor current, the PWM controller
has a single pole. The pole frequency and DC gain of
the PWM controller are dependent on the operating
duty cycle, which is:
f C =
Z O
3
=
1
6 π C OUT E SR
D = (2 L f OSC / R E )1/2
where R E is the equivalent load resistance, or:
f C = SW
or 1/5 of the switching frequency:
f
5
whichever is lower.
2) Determine the pole frequency due to the output
capacitor and the load resistor:
R E = V IN 2 R LOAD / (V OUT (V OUT - V IN ))
The frequency of single pole due to the PWM converter
is:
P O = (2 V OUT - V IN ) / (2 π (V OUT - V IN ) R LOAD C OUT )
and the DC gain of the PWM controller is:
or
P O =
1
2 π R LOAD ( MIN ) C OUT
A VO = 2 V OUT (V OUT - V IN ) R LOAD / ((2 V OUT - V IN ) D)
Note that, as in the current-mode, step-down cases
above, as R LOAD is increased, the pole frequency
decreases and the DC gain increases proportionally.
Since the crossover frequency is the product of the
P O =
I LOAD ( MAX )
2 π V OUT C OUT
pole frequency and the DC gain, it remains indepen-
dent of the load.
20 M ? f C
3) Determine the compensation resistor required to set
the desired crossover frequency:
R C =
A VDC P O
or, by simplifying and using the typical V REF = 1.25V:
R C = 50k ? /V V OUT C OUT f C
4) Determine the compensation capacitor to set the
proper error-amplifier pole and zero determined from
the above equations:
As in the cases of the main and core converters, the gain
through the voltage-divider is A VDV = V REF / V OUT , and
the DC gain of the error amplifier is A VEA = 2000V/V.
Thus, the DC loop gain is A VDC = A VDV A VEA A VO .
The compensation resistor-capacitor pair at COMP
cause a pole and zero at frequencies (in Hz):
P C = G EA / (4000 π C C ) = 1 / (4x107 π C C )
Z C = 1 / (2 π R C C C )
and the ESR of the output filter capacitor causes a zero
in the loop response at the frequency (in Hz): Z O = 1 /
(2 π C OUT ESR).
The DC gain and the poles and zeros are shown in the
C C =
1
2 π R C P O
Bode plot of Figure 7. To achieve a stable circuit with
the Bode plot of Figure 7, follow the procedure below:
1) Choose the R C that is equivalent to the inverse of
Auxiliary Controllers
The auxiliary controllers use voltage mode to regulate
their output voltages. The following explains how to
compensate the control system for optimal perfor-
the transconductance of the error amplifier, 1 / R C =
G EA = 100μs, or R C = 10k ? . This sets the high-fre-
quency voltage gain of the error amplifier to 0dB.
2) Determine the maximum output pole frequency:
mance. The compensation differs depending on
whether the inductor current is continuous or discontin-
uous.
P O(MAX) =
2V OUT ? V IN
2 π ( V OUT ? V IN ) R LOAD ( MIN ) C OUT
where R LOAD(MIN) = V OUT / I OUT(MAX) .
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23
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