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| 型号： | MAX1809ETI+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 11/17页 |
| 文件大小： | 0K |
| 描述： | IC DDR TERMINATION 28-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 转换器，DDR |
| 输入电压： | 3 V ~ 5.5 V |
| 输出数： | 1 |
| 输出电压： | 1.1 V ~ 5.5 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-QSOP |
| 包装： | 带卷 (TR) |
3A, 1MHz, DDR Memory Termination Supply
V OUT = V EXTREF
V DDQ
LX
LX
V OUT
MAX1809
MAX1809
R2
V EXTREF
EXTREF
FB
EXTREF
FB
(1.1V ≤ V EXTREF ≤ V IN - 1.7V)
Figure 5. Adjusting the Output Voltage Using EXTREF
The output current limit during soft-start varies with
the voltage on the soft-start pin, SS, according to the
equation:
R1
R2 = R1[(V OUT / V EXTREF ) - 1]
Figure 6. Adjusting the Output Voltage at FB
careful component placement, and correct routing of
traces using appropriate trace widths. The following
points are in order of decreasing importance:
1) Minimize switched-current and high-current ground
I LIM ( SS ) =
V SS ? 0.7V
1 . 1 V
× I LIMIT
loops. Connect the input capacitor ’ s ground, the
output capacitor ’ s ground, and PGND close together.
Connect the resulting PGND plane to GND at only
( V IN ? V OUT ? V PMOS )
t OFF ( V IN PMOS NMOS )
f SW =
where I LIMIT is the current-limit threshold from the
Electrical Characteristics . The constant-current source
stops charging once the voltage across the soft-start
capacitor reaches 1.8V.
Applications Information
Frequency Variation with Output Current
The operating frequency of the MAX1809 is determined
primarily by t OFF (set by R TOFF ), V IN , and V OUT as
shown in the following formula:
? V + V
However, as the output current increases, the voltage
drop across the NMOS and PMOS switches increases
and the voltage across the inductor decreases. This
causes the frequency to drop. Assuming R PMOS =
R NMOS , the change in frequency can be approximated
with the following formula:
one point.
2) Connect the input filter capacitor less than 5mm
away from IN. The connecting copper trace carries
large currents and must be at least 1mm wide,
preferably 2.5mm.
3) Place the LX node components as close together
and as near to the device as possible. This reduces
resistive and switching losses as well as noise.
4) Ground planes are essential for optimum perfor-
mance. In most applications, the circuit is located on
a multilayer board and full use of the four or more
layers is recommended. For heat dissipation, con-
nect the exposed backside pad of the QFN pack-
age to a large analog ground plane, preferably on a
surface of the board that receives good airflow. If
the ground plane is located on the top layer, make
use of the N.C. pins adjacent to GND to lower thermal
resistance to the ground plane. If the ground is
located elsewhere, use several vias to lower thermal
resistance. Typical applications use multiple ground
? f SW =
? I OUT × R PMOS
( V IN × t OFF )
planes to minimize thermal resistance. Avoid large
AC currents through the analog ground plane.
Voltage Positioning
where R PMOS is the resistance of the internal MOSFETs
(90m ? typ).
Circuit Layout and Grounding
Good layout is necessary to achieve the MAX1809 ’ s
intended output power level, high efficiency, and low
noise. Good layout includes the use of ground planes,
In applications where the load transients are extremely
fast (>10A/μs), the total output capacitance has to be
large enough to handle the V SAG and V SOAR require-
ments while keeping within the output tolerance limits.
Voltage positioning reduces the total amount of output
capacitance needed to meet a given transient
response requirement. With voltage positioning, the
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