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| 型号： | MAX1809ETI+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 12/17页 |
| 文件大小： | 0K |
| 描述： | IC DDR TERMINATION 28-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 转换器，DDR |
| 输入电压： | 3 V ~ 5.5 V |
| 输出数： | 1 |
| 输出电压： | 1.1 V ~ 5.5 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-QSOP |
| 包装： | 带卷 (TR) |
3A, 1MHz, DDR Memory Termination Supply
output regulates at a slightly lower voltage under a
given load, allowing more voltage headroom as the
load changes suddenly to zero or to the opposite polarity
(sinking mode). By utilizing the full-voltage tolerance lim-
its, the total output capacitance can be reduced and the
SHDN
0
1.8V
capacitor ’ s ESR can be increased.
Choose R DROOP such that the output voltage at the
V SS (V)
0
0.7V
maximum load current, including ripple, is just above
the lower limit of the output tolerance.
R DROOP ? I OUT(MAX) ≤ V OUT(TYP) - V OUT(MIN) -
(V RIPPLE / 2)
I LIMIT (A)
0
I LIMIT
t
Voltage positioning results in some loss in efficiency
due to the power dissipated in R DROOP . The maximum
power loss is given by R DROOP ? I OUT(MAX) 2 . R DROOP
must be able to handle this power.
Figure 7. Soft-Start Current Limit Over Time
- DDQ
Ceramic Output Capacitor Applications
Ceramic capacitors have advantages and disadvan-
tages. They have ultra-low ESR and are noncom-
bustible, relatively small, and nonpolarized. They are
also expensive and brittle, and their ultra-low ESR char-
acteristic can result in excessively low output-voltage
ripple (affecting stability in nonvoltage-positioned cir-
cuits). In addition, their relatively low capacitance value
can cause output overshoot when going abruptly from
full-load sourcing to full-load sinking conditions, unless
V DDQ
V OUT
(MAX1809)
+
LINE RECEIVERS
COMMON BUS
TERMINATION RESISTOR
V /2 = V TT
the inductor value can be made small (high switching
frequency), or there are some bulk tantalum or elec-
trolytic capacitors in parallel to absorb the stored energy
in the inductor. In some cases, there may be no room for
electrolytics, creating a need for a DC-DC design that
uses nothing but ceramics.
The MAX1809 can take full advantage of the small size
and low ESR of ceramic output capacitors in a voltage-
positioned circuit. The addition of the positioning resis-
tor increases the ripple at FB, satisfying the minimum
feedback ripple voltage requirement.
Output overshoot (V SOAR ) determines the minimum
output capacitance requirement (see the Output
Capacitor Selection ). Often the switching frequency is set
as high as possible (near 1000kHz), and the inductor
value is reduced to minimize the energy transferred from
inductor to capacitor during load-step recovery.
Input Source
The output of the MAX1809 can accept current due to
the reversible properties of the buck and the boost con-
verter. When voltage at the output of the MAX1809
(low-voltage port) exceeds or equals the output set
voltage the flow of energy reverses, going from the out-
put to the input (high-voltage port). If the input (high-
voltage port) is not connected to a low-impedance
Figure 8. Active Bus Termination
source capable of absorbing energy, the voltage at the
input will rise. This voltage can violate the absolute maxi-
mum voltage at the input of the MAX1809 and destroy
the part. This occurs when sinking current because the
topology acts as a boost converter, pumping energy
from the low-voltage side (the output), to the high-voltage
side (the input). The input (high-voltage side) voltage is
limited only by the clamping effect of the voltage source
connected there. To avoid this problem, make sure the
input to the MAX1809 is connected to a low impedance,
two quadrant supply or that the load (excluding the
MAX1809) connected to that supply consumes more
power than the amount being transferred from the
MAX1809 output to the input.
Active Bus Termination
DDR memory architecture is a high-speed system that
clocks data on both the rising and falling edges of the
clock. This increases the data rate, and at the same
time increases the system power dissipation. High-
speed digital logic requires termination of the buses to
minimize ringing and reflection. Using an active termi-
nation scheme reduces the power dissipation of the
bus. By connecting the termination resistors to a supply
voltage (V TT ) that is half the memory voltage (V DDQ ),
12
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