参数资料
型号: MAX1845ETX+T
厂商: Maxim Integrated Products
文件页数: 22/27页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 36-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 电流模式
输出数: 2
频率 - 最大: 540kHz
电源电压: 4.5 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 36-WFQFN 裸露焊盘
包装: 带卷 (TR)
Dual, High-Efficiency, Step-Down
Controller with Accurate Current Limit
OUT1
OUT2
V BATT
2.5V
FIXED
1.5V
TO ERROR
AMP1
TO ERROR FIXED
AMP2
DH_
FIXED
1.8V
MAX1845
DL_
V OUT
CS_
FB1
2V
0.1V
FB2
OUT_
FB_
R1
R2
MAX1845
0.1V
Figure 8. Feedback Mux
mount all of the power components on the top side of
GND
Figure 9. Setting V OUT with a Resistor-Divider
the board, with connecting terminals flush against one
another.
USE AGND PLANE TO:
- BYPASS V CC AND REF
- TERMINATE EXTERNAL FB, ILIM,
USE PGND PLANE TO:
- BYPASS V DD
- CONNECT IC GROUND
Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable,
OVP DIVIDERS, IF USED
- PIN-STRAP CONTROL
INPUTS
AGND PLANE
TO TOP-SIDE STAR GROUND
jitter-free operation. Short power traces and load con-
nections are essential for high efficiency. Using thick
copper PC boards (2oz vs. 1oz) can enhance full-load
efficiency by 1% or more. Correctly routing PC board
traces is a difficult task that must be approached in
terms of fractions of centimeters, where a single mil-
liohm of excess trace resistance causes a measurable
efficiency penalty.
Place the current-sense resistors close to the top-side
star-ground point (where the IC ground connects to the
PGND PLANE
AGND PLANE
VIA TO TOP-SIDE
GROUND
top-side ground plane) to minimize current-sensing
errors. Avoid additional current-sensing errors by using
a Kelvin connection from CS_ pins to the sense resis-
Q1
V IN
Q3
tors.
The following guidelines are in order of importance:
? Keep the space between the ground connection of
Q2
C IN C IN C IN
Q4
the current-sense resistors short and near the via to
the IC ground pin.
? Minimize the resistance on the low-side path. The
low-side path starts at the ground of the low-side
L1
D1
C1
D2
C2
L2
FET, goes through the low-side FET, through the
inductor, through the output capacitor, and returns
to the ground of the low-side FET. Minimize the resis-
tance by keeping the components close together
and the traces short and wide.
VIA TO OUT1
NOTCH
VIA TO CS1
VIA TO PGND PLANE AND IC GND
TOP-SIDE GROUND PLANE
? Minimize the resistance in the high-side path. This
path starts at V IN , goes through the high-side FET,
Figure 10. PC Board Layout Example
22
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