参数资料
型号: MAX1858EEG+T
厂商: Maxim Integrated Products
文件页数: 16/21页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 24-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 电压模式
输出数: 2
频率 - 最大: 660kHz
占空比: 90%
电源电压: 4.75 V ~ 23 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 24-SSOP(0.154",3.90mm 宽)
包装: 带卷 (TR)
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
GAIN = +V IN /V RAMP FOR
FREQUENCIES LOWER
P
DH
N
THAN NYQUIST
W
L
V OUT
L
COMP_
V C
g M_GROUP
M
DL
FB
N
LX
R ESR
C OUT
=
COMP_
g M_GROUP
FB
LX
R ESR
C OUT
R COMP_
C COMP_A
C COMP_B
V SET
R COMP_
C COMP_A
C COMP_B
V SET
Figure 7. Fixed-Frequency Voltage-Mode Control Loop
? R COMP has much higher impedance than C COMP_A .
This is true if, and only if, crossover occurs above
f Z_COMP_A . If this is true, C COMP_A can be ignored
(as a short to ground).
? R ESR is much higher impedance than C OUT . This is
true if, and only if, crossover occurs well after the out-
put capacitor ’ s ESR zero. If this is true, C OUT
? Unity-gain crossover must occur below 1/5th of the
switching frequency.
? For reasonable phase margin using type 1 compen-
sation, f CO must be larger than 5 ? f ESR .
Choose C COMP_A so that f Z_COMP_A equals half f LC
using the following equation:
becomes an insignificant part of the loop gain and can
be ignored (as a short to ground).
? C COMP_B is much higher impedance than R COMP
C COMP _ A =
2 × LC OUT
R COMP
and can be ignored (as an open circuit). This is true
if, and only if, crossover occurs far below f COMP_B .
Choose C COMP_B so that f COMP_B occurs at 3 times
f CO using the following equation:
The following loop-gain equation can be found by using
these previous approximations with Figure 7:
V IN V SET g M _ COMP × R COMP × R ESR
A L ? × ×
V RAMP V OUT sL
C COMP _ B =
1
2 π × ( 3 × f CO ) × R COMP
MOSFET Selection
Setting the loop gain to 1 and solving for the crossover
frequency yields:
The MAX1858 ’ s step-down controller drives two exter-
nal logic-level N-channel MOSFETs as the circuit switch
elements. The key selection parameters are:
× SET
f CO = GBW =
V IN
V RAMP
V
V OUT
? On-resistance (R DS(ON) )
? Maximum drain-to-source voltage (V DS(MAX) )
×
g M _ COMP × R COMP × R ESR
2 π × L
? Minimum threshold voltage (V TH(MIN) )
? Total gate charge (Q g )
? Reverse transfer capacitance (C RSS )
To ensure stability, select R COMP to meet the following
criteria:
? Power dissipation
16
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