参数资料
型号: MAX1937EEI+T
厂商: Maxim Integrated Products
文件页数: 17/24页
文件大小: 0K
描述: IC REG CTRLR PWM HYBRID 28-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 混合物
输出数: 1
频率 - 最大: 500kHz
占空比: 50%
电源电压: 6 V ~ 24 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 85°C
封装/外壳: 28-QSOP
包装: 带卷 (TR)
Two-Phase Desktop CPU Core Supply
Controllers with Controlled VID Change
VOLTAGE POSITIONING THE OUTPUT
I PEAK
I LOAD
I VALLEY
1.4V
1.4V
A. CONVENTIONAL CONVERTER (50mV/div)
A
B
TIME
Figure 2. Inductor Current Waveform
The maximum allowable voltage change during a tran-
sient is fixed by the supply range of the CPU (V P-P1 =
V P-P2 ). This means that the voltage-positioned circuit
tolerates twice the ESR in the output capacitors.
Because the ESR specification is achieved by parallel-
ing several capacitors, fewer capacitors are needed for
the voltage-positioned circuit. Figure 4 shows transient
response regions.
An additional benefit of voltage positioning is reduced
power consumption at high-load currents. Because the
output voltage is lower under heavy load, the CPU
draws less current. The result is lower power dissipa-
tion in the CPU.
Voltage Reference (REF)
A 2V reference is provided on the MAX1937/MAX1938/
MAX1939 through the REF pin. REF is capable of
sourcing or sinking up to 50μA. In addition to providing
a reference for the IC, REF is used for setting the cur-
rent limit and voltage positioning. Connect a 0.47μF
capacitor from REF to GND. This capacitor should be
placed as close as possible to the REF pin.
A UVLO is provided for the reference voltage. The ref-
erence voltage must rise above 1.600V to activate the
controller. The controller is disabled if the reference
voltage falls below 1.584V.
Enable Input (EN) and Soft-Start
When EN is low, DL_ and DH_ are held low (turning off
the MOSFETs), leaving LX_ high impedance. In addi-
tion, the reference is turned off and PWRGD is pulled
low. In shutdown, total current consumption is about
50μA (typ).
B. VOLTAGE-POSITIONED OUTPUT (50mV/div)
Figure 3. Voltage-Positioning and Nonvoltage-Positioning
Waveforms
In the case of shutdown by VID code, only DL_ and
DH_ are held low. The rest of the controller is enabled.
When EN is driven high, the startup sequence begins.
Once the reference voltage rises above its 1.6V UVLO
threshold, the controller begins switching and starts to
ramp up the output voltage. The output voltage is
ramped up in 25mV steps every 50μs until the output
reaches the nominal output voltage.
Fault Conditions
The MAX1937/MAX1938/MAX1939 contain internal cir-
cuitry to protect themselves and surrounding circuitry
from damage from output overvoltage and output
undervoltage conditions. When either of these condi-
tions occurs, DH_ is pulled low, DL_ is driven high, and
PWRGD is pulled low. These pins remain in this state
until either power is cycled on V DD or EN is toggled
high-low-high.
Setting the Output Voltage (VID_)
An internal DAC is used to set the output regulation
voltage. A 5-bit code on inputs VID0–VID4 is used to
specify the output voltage. Some codes disable the
output. There is an internal 100k Ω pullup resistor to
VDD on each of the VID_ inputs. Connecting VID_ to
GND sets the bit to logic low (0); connecting VID_ to
VDD or leaving it unconnected sets the bit to logic high
(1). Use external pullup resistors to speed the low-to-
high logic transition, or for lower logic voltages. See
Table 1 for a list of codes and corresponding output
regulation voltages for each of the parts.
The VID_ codes for the MAX1937 comply with AMD
Hammer code. The VID_ codes on the MAX1938 are
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