参数资料
型号: MAX1937EEI+T
厂商: Maxim Integrated Products
文件页数: 18/24页
文件大小: 0K
描述: IC REG CTRLR PWM HYBRID 28-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 混合物
输出数: 1
频率 - 最大: 500kHz
占空比: 50%
电源电压: 6 V ~ 24 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 85°C
封装/外壳: 28-QSOP
包装: 带卷 (TR)
Two-Phase Desktop CPU Core Supply
Controllers with Controlled VID Change
CAPACITIVE SOAR
Design Procedure
V OUT
ESR VOLTAGE STEP
(I STEP x R ESR )
(dV/dt = I OUT /C OUT )
Output Inductor Selection
For most applications, an inductor value of 0.5μH to
1μH is recommended. The inductance is set by the
desired amount of inductor current ripple (LIR). A larger
inductance value minimizes output ripple current and
increases efficiency, but slows transient response. For
the best compromise of size, cost, and efficiency, a LIR
of 30% to 40% is recommended (LIR = 0.3 to 0.4). The
CAPACITIVE SAG
(dV/dt = I OUT /C OUT )
RECOVERY
inductor value is found from:
( )
L =
V OUT × V IN ? V OUT
V IN × f SW × I LOAD ( MAX ) × LIR
I LOAD
where f sw is the actual switching frequency of a phase.
Figure 4. Transient Response Regions
set for Intel VRM 9.0/9.1 and AMD Athlon. The
MAX1939 is set for AMD Athlon Mobile.
The selected inductor should have the lowest possible
equivalent DC resistance and a saturation current
greater than the peak inductor current (I PEAK ). I PEAK is
found from:
I PEAK = I LOAD ( MAX ) × ? 1 +
2 ?
VID_ Change Slew Rate (TIME)
The MAX1937/MAX1938/MAX1939 allow the VID_ code
to be changed while the converter is operating (on-the-
fly). The slew rate at which the output voltage is chang-
?
?
LIR ?
?
ing is controlled through TIME. The slew rate is
adjusted externally by connecting a 47k Ω to 470k Ω
resistor (R TIME ) from TIME to GND. To set the slew rate,
select the R TIME resistor using the following equation:
Output Capacitor Selection
The output capacitor must have low enough ESR to
meet output ripple and load-transient requirements.
Also, the capacitance value must be high enough to
R TIME =
521
SR
( Ω )
absorb the inductor energy going from a full-load to a
no-load condition without tripping the OVP circuit.
In CPU core power supplies and other applications
where SR is the slew rate of the output voltage in V/μs.
The output voltage is stepped up or down in 25mV
steps until it reaches the voltage set by the new VID
code.
Power-Good Output (PWRGD)
PWRGD is an open-drain output that is pulled low when
the output voltage deviates more than 12.5% from its
regulation voltage (set by VID_ inputs). PWRGD is
pulled low in shutdown, input UVLO, and during start-
up. Any fault condition forces PWRGD low until the fault
is cleared, and the IC is reset by cycling power at V DD
or momentarily toggling EN. For logic-level output volt-
ages, connect an external pullup resistor between
PWRGD and the logic power supply. A 100k Ω resistor
works well in most applications.
where the output is subject to large load transients, the
output capacitor’s size typically depends on how much
ESR is needed to prevent the output from dipping too
low under a load transient. Ignoring the sag due to
finite capacitance:
R ESR = V STEP(MAX) / Δ I LOAD(MAX)
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as to
the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of OS-
CONs, SP capacitors, POSCAPs, and other electrolytic
capacitors). Generally, ceramic capacitors are not rec-
ommended for bulk output capacitance but make
excellent high-frequency decoupling capacitors.
Once enough capacitance is added to meet the over-
shoot requirement, undershoot at the rising load edge
18
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