参数资料
型号: MAX194BEWE+T
厂商: Maxim Integrated Products
文件页数: 10/24页
文件大小: 0K
描述: IC ADC 14BIT 85KSPS 16-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1,000
位数: 14
采样率(每秒): 85k
数据接口: QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 80mW
电压电源: 模拟和数字,双 ±
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 带卷 (TR)
输入数目和类型: 1 个单端,单极;1 个单端,双极
MAX194
Complete source code for the Motorola 68HC16 and
the MAX194 evaluation kit (EV kit) using this mode is
available in the MAX194 EV kit manual.
Mode 2 (Asynchronous Data Transfer)
This mode uses a conversion clock (CLK) and a serial
clock (SCLK). The serial data is clocked out between
conversions, which reduces the maximum throughput
for high CLK rates, but may be more convenient for
some applications. Figure 19 is a block diagram with a
QSPI processor (Motorola 68HC16) connected to the
MAX194. Figure 20 shows the associated timing dia-
gram. Figure 21 gives an assembly language listing for
this arrangement.
An OR gate is used to synchronize the “start” signal to
the asynchronous CLK, as described in the
External
Clock section. As with Mode 1, the QSPI processor must
run CLK during calibration and either count CLK cycles
or, as is done here, monitor EOC to determine when cal-
ibration is complete. Also, EOC is polled by the P to
determine when a conversion result is available. When
EOC goes low, data is clocked out at the highest QSPI
data rate (4.19Mbps). After the data is transferred, a
new conversion can be initiated whenever desired.
The timing specification for SCLK-to-DOUT valid (tSD)
imposes some constraints on the serial interface. At
SCLK rates up to 2.5Mbps, data is clocked out of the
MAX194 by a falling edge of SCLK and may be
clocked into the P by the next rising edge (CPOL = 0,
CPHA = 0). For data rates greater than 2.5Mbps (or for
lower rates, if desired) it is necessary to clock data out
of the MAX194 on SCLK’s falling edge and to clock it
into the P on SCLK’s next falling edge (CPOL = 0,
CPHA = 1). Also, your processor hold time must not
exceed tSD minimum (20ns). As with CLK in mode 1,
maximum SCLK rates may not be possible with some
interface specifications that are subsets of SPI.
Supplies, Layout, Grounding
and Bypassing
For best system performance, use printed circuit boards
with separate analog and digital ground planes. Wire-
wrap boards are not recommended. The two ground
planes should be tied together at the low-impedance
power-supply source and at the MAX194, as shown in
Figure 22. If the analog and digital supplies come from
the same source, isolate the digital supply from the ana-
log supply with a low-value resistor (10
).
14-Bit, 85ksps ADC with 10A Shutdown
18
______________________________________________________________________________________
CS
CLK
START
588ns
239ns
CONVERSION TIME
4.19MHz
1.3
s
9.4
s
17
s
5.1
s
4
s
EOC
SCLK
DOUT
B13
B1 B0
B11
B12
S1
S0
Figure 20. Timing Diagram for Circuit of Figure 19
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