参数资料
型号: MAX194BEWE+T
厂商: Maxim Integrated Products
文件页数: 22/24页
文件大小: 0K
描述: IC ADC 14BIT 85KSPS 16-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1,000
位数: 14
采样率(每秒): 85k
数据接口: QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 80mW
电压电源: 模拟和数字,双 ±
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 带卷 (TR)
输入数目和类型: 1 个单端,单极;1 个单端,双极
If the power supplies do not settle within the MAX194’s
power-on delay (500ns minimum), power-up calibration
may begin with supply voltages that differ from the final
values and the converter may not be properly calibrat-
ed. If so, recalibrate the converter (pulse RESET low)
before use. For best DC accuracy, calibrate the
MAX194 any time there is a significant change in sup-
ply voltages, temperature, reference voltage, or clock
characteristics (see
External Clock section) because
these parameters affect the DC offset. If linearity is the
only concern, much larger changes in these parame-
ters can be tolerated.
Because the calibration data is stored digitally, there is
no need either to perform frequent conversions to main-
tain accuracy or to recalibrate if the MAX194 has been
held in shutdown for long periods. However, recalibra-
tion is recommended if it is likely that supply voltages or
ambient temperature has significantly changed since
the previous calibration.
Digital Interface
The digital interface pins consist of BP/UP/SHDN, CLK,
SCLK, EOC, CS, CONV, and RESET.
BP/UP/SHDN is a three-level input. Leave it floating to
configure the MAX194’s analog input in bipolar mode
(AIN = -VREF to VREF) or connect it high for a unipolar
input (AIN = 0V to VREF). Bringing BP/UP/SHDN low
places the MAX194 in its 10A shutdown mode.
A logic low on RESET halts MAX194 operation. The ris-
ing edge of RESET initiates calibration as described in
the
Calibration section above.
Begin a conversion by bringing CONV low. The convert
signal must be synchronized with CLK. The falling edge
of CONV must occur during the period shown in
Figures 3 and 4. When CLK is not directly controlled by
your processor, two methods of ensuring synchroniza-
tion are to drive CONV from EOC (continuous conver-
sions) or to gate the conversion-start signal with the
conversion clock so that CONV can go low only while
CLK is low (Figure 5). Ensure that the maximum propa-
gation delay through the gate is less than 40ns.
The MAX194 automatically ensures four CLK periods
for track/hold acquisition. If, when CONV is asserted, at
least three clock (CLK) cycles have passed since the
end of the previous conversion, a conversion will begin
on CLK’s next falling edge and EOC will go high on the
following falling CLK edge (Figure 3). After conversion
begins, additional convert start pulses are ignored. If,
when convert is asserted, less than three clock cycles
have passed, a conversion will begin on the fourth
falling clock edge after the end of the previous conver-
MAX194
14-Bit, 85ksps ADC with 10A Shutdown
_______________________________________________________________________________________
7
TRACK/HOLD
CLK
CONVERSION
BEGINS
CONVERSION
ENDS
tAQ
*
* THE FALLING EDGE OF CONV MUST OCCUR IN THIS REGION
tCEL
tCW
tCEH
tCC2
tCC1
EOC
CONV
Figure 3. Initiating Conversions—At least 3 CLK cycles since end of previous conversion.
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