参数资料
型号: MAX1980ETP+
厂商: Maxim Integrated Products
文件页数: 5/33页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 20-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
系列: Quick-PWM™
PWM 型: 控制器
输出数: 1
频率 - 最大: 550kHz
占空比: 50%
电源电压: 4.5 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 85°C
封装/外壳: 20-WQFN 裸露焊盘
包装: 管件
Quick-PWM Slave Controller with
Driver Disable for Multiphase DC-DC Converter
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V CC = V DD = 5V, V OUT = V COMP = 1.2V, V CM+ = V CM- = V CS+ = V CS- = 1.2V, DD = V CC , T A = -40 ° C
to +100 ° C , unless otherwise noted.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CURRENT SENSING
On-Time Adjustment Range
0.42V < V COMP < 2.8V, V OUT ≥ 0.7V
-40
+40
%
COMP Output Current
I COMP
Sink and source
30
μA
Current-Balance Offset
Current-Sense, Common-Mode
Range
(V CM+ - V CM- ) - (V CS+ - V CS- ), I COMP = 0,
-100mV ≤ (V CM+ - V CM- ) ≤ +100mV
CM+, CM-, CS+, CS-
-2.0
-0.2
+2.0
+2.0
mV
V
Positive Current-Limit Threshold
Negative Current-Limit
Threshold
V C_LIM
V CM+ - V CM- and
V CS+ - V CS-
V CS+ - V CS-
V ILIM = 0.5V
V ILIM = 1V
V ILIM = 0.5V
V ILIM = 1V
47.5
97
-80
-160
52.5
103
-70
-140
mV
mV
ILIM Standby Threshold Voltage
0.2
0.3
V
FAULT PROTECTION
V CC Undervoltage Lockout
Threshold
Rising edge, hysteresis = 20mV, switching
disabled below this level
3.45
3.90
V
GATE DRIVERS
DH Gate-Driver On-Resistance
(Note 3)
DL Gate-Driver On-Resistance
(Note 3)
R ON(DH)
R ON(DL)
V BST - V LX forced to 5V
High state (pullup)
Low state (pulldown)
4.5
4.5
2.0
?
?
LOGIC
TRIG Logic Levels
V TRIG
350mV hysteresis
High
Low
3.0
1.2
V
Logic high (V CC ; 200kHz operation)
V CC - 0.4
TON Logic Levels
V TON
Open (300kHz operation)
1.6
3.1
V
Logic low (GND; 550kHz operation)
0.5
Note 1: On-time specifications are measured from 50% point to 50% point at the DH pin with LX = PGND, V BST = 5V, and a 500pF
capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times may be different due to
MOSFET switching speeds.
Note 2: The trigger delay time, t TRIG , is measured from the time the TRIG pin transitions to the time when the DL pin goes low.
Note 3: Production testing limitations due to package handling require relaxed maximum on-resistance specifications for the QFN
package.
Note 4: The driver-disable delay time (t DD ) is measured from the time the DD pin transitions to the time when the DL or DH pin tran-
sitions.
Note 5: Specifications to -40 ° C and +100 ° C are guaranteed by design and not production tested.
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