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| 型号： | MAX2079CXE+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 26/49页 |
| 文件大小： | 0K |
| 描述： | IC OCT ULTRASOUND RCVR 144CTBGA |
| 标准包装： | 1,000 |
| 系列： | * |
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Low-Power, High-Performance, Fully Integrated
Octal Ultrasound Receiver (Octal LNA, VGA,
AAF, ADC, and CWD Beamformer)
MAX2079
32
Maxim Integrated
Clock Output (CLKOUT+, CLKOUT-)
The ADC provides a differential clock output that consists
of CLKOUT+ and CLKOUT-. As shown in Figure 19, the
serial-output data is clocked out of the device on both
edges of the clock output. The frequency of the output
clock is six times (6x) the frequency of the input clock.
The Output Data Format and Test Pattern/Digital HPF
Select register (01h) allows the phase of the clock output
to be adjusted relative to the output data frame (Table 7,
Frame-Alignment Output (FRAME+, FRAME-)
The ADC provides a differential frame-alignment signal
that consists of FRAME+ and FRAME-. As shown in
Figure 18, the rising edge of the frame-alignment signal
corresponds to the first bit (D0) of the 12-bit serial-data
stream. The frequency of the frame-alignment signal is
identical to the frequency of the input clock; however, the
duty cycle varies depending on the input clock frequency.
Serial-Output Data (OUT_+, OUT_-)
The ADC provides conversion results through individual
differential outputs consisting of OUT_+ and OUT_-. The
results are valid 10.5 input clock cycles after a sample is
taken. As shown in Figure 19, the output data is clocked
out on both edges of the output clock, LSB (D0) first (by
default). Figure 18 displays the detailed serial-output
timing diagram.
Differential LVDS Digital Outputs
The ADC features programmable, fully differential LVDS
digital outputs. By default, the 12-bit data output is trans-
mitted LSB first, in offset binary format. The Output Data
Format and Test Pattern/Digital HPF Select register (01h,
Table 7) allows customization of the output bit order and
data format. The output bit order can be reconfigured
to transmit MSB first, and the output data format can be
changed to two’s complement. Table 8 contains full out-
put data configuration details.
The LVDS outputs feature flexible programming options.
First, the output common-mode voltage can be pro-
grammed from 0.6V to 1.2V (default) in 200mV steps
(Table 15). Use the LVDS Output Driver Level register (02h,
Table 11) to adjust the output common-mode voltage.
The LVDS output driver current is also fully programma-
ble through the LVDS Output Driver Management register
(03h, Table 16). By default, the output driver current is set
to 3.5mA. The output driver current can be adjusted from
0.5mA to 7.5mA in 0.5mA steps (Table 17).
The LVDS output drivers also feature optional internal
terminations that can be enabled and adjusted by the
LVDS Output Driver Management register (03h, Table 16).
By default, the internal output driver termination is dis-
abled. See Table 18 for all possible configurations.
Output Driver Level Tests
The LVDS outputs (data, clock, and frame) can be
configured to static logic-level test states through the
LVDS Output Driver Level register (02h, Table 11). The
complete list of settings for the static logic-level test
Data Output Test Patterns
The LVDS data outputs can be configured to output
several different, recognizable test patterns. Test patterns
are enabled and selected using the Output Data Format
and Test Pattern/Digital HPF Select register (01h, Table 7).
A complete list of test pattern options are listed in Table 9,
and custom test pattern details can be found in the
Custom Test Pattern registers (07h, 08h, 09h) section
Power Management
The SHDN input is used to toggle between two power-
management states. Power state 0 corresponds to SHDN
= 0, while power state 1 corresponds to SHDN = 1. The
PLL Sampling Rate and Power Management register
(00h) and the Channel Power Management registers (05h
and 06h) fully define each power-management state. By
default, SHDN = 1 shuts down the device, and SHDN =
0 returns the ADCs to full-power operation. Use of the
SHDN input is not required for power management.
For either state of SHDN, complete power-manage-
ment flexibility is provided, including individual ADC
channel power-management control, as well as the
option of which reduced power-mode to utilize in each
power state. The reduced-power modes available are
Figure 19. Serial Output Detailed Timing Diagram
tOD
tCH
tOD
D0
D1
D2
D3
D4
tCL
CLKOUT+
- CLKOUT-
OUT_+
- OUT_-
tCH—CLKOUT_ OUTPUT- WIDTH HIGH
tCL—CLKOUT_ OUTPUT- WIDTH LOW
tOD—DATA VALID TO CLKOUT_ RISE/FALL
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