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参数资料
| 型号： | MAX2112CTI+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 10/19页 |
| 文件大小： | 0K |
| 描述： | IC TUNER DIR-CONV DVB-S2 28-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 频率： | 925MHz ~ 2.175GHz |
| 应用： | 数字 TV，CATV，机顶盒 |
| 电流 - 接收： | 100mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 电源电压： | 3.13 V ~ 3.47 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
MAX2112
Complete, Direct-Conversion
Tuner for DVB-S2 Applications
Table 2. N-Divider MSB Register
BIT NAME
BIT LOCATION (0 = LSB) DEFAULT
FUNCTION
FRAC
N[14:8]
7
6–0
1
0000000
Users must program to 1 upon powering up the device.
Sets the most significant bits of the PLL integer-divide number (N). N can
range from 19 to 251.
Table 3. N-Divider LSB Register
BIT NAME
N[7:0]
BIT LOCATION (0 = LSB)
7 –0
DEFAULT
00100011
FUNCTION
Sets the least significant bits of the PLL integer-divide number. N can range
from 19 to 251.
Table 4. Charge-Pump Register
BIT NAME
BIT LOCATION (0 = LSB) DEFAULT
FUNCTION
CPMP[1:0]
CPLIN[1:0]
F[19:16]
7–6
5–4
3–0
00
00
0010
Charge-pump minimum pulse width. Users must program to 00 upon
powering up the device.
Controls charge-pump linearity. Users must program to 01 upon powering up
the device.
Sets the 4 most significant bits of the PLL fractional divide number.
Default value is F = 194,180 decimal.
Table 5. F-Divider MSB Register
BIT NAME
BIT LOCATION (0 = LSB) DEFAULT
FUNCTION
F[15:8]
7–0
11110110
Sets the most significant bits of the PLL fractional-divide number (F).
Default value is F = 194,180 decimal.
Table 6. F-Divider LSB Register
BIT NAME
BIT LOCATION (0 = LSB) DEFAULT
FUNCTION
F[7:0]
7–0
10000100
Sets the least significant bits of the PLL fractional-divide number (F).
Default value is F = 194,180 decimal.
Table 7. XTAL Buffer and Reference Divider Register
BIT NAME
BIT LOCATION (0 = LSB) DEFAULT
Sets the crystal-divider setting.
000 = Divide by 1.
001 = Divide by 2.
FUNCTION
XD[2:0]
7–5
000
011 = Divide by 3.
100 = Divide by 4.
101 through 110 = All divide values from 5 (101) to 7 (110).
111 = Divide by 8.
Sets the PLL reference-divider (R) number. Users must program to 00001
R[4:0]
4–0
00001
upon powering up the device.
00001 = Divide by 1; other values are not tested.
10
Maxim Integrated
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