参数资料
型号: MAX2120EVKIT+
厂商: Maxim Integrated
文件页数: 10/21页
文件大小: 0K
描述: KIT EVAL FOR MAX2120
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
类型: 调谐器
频率: 925MHz ~ 2.175GHz
适用于相关产品: MAX2120
已供物品:
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
Detailed Description
Register Description
The MAX2120 includes 12 user-programmable registers
and 2 read-only registers. See Table 1 for register con-
Table 1. Register Configuration
MSB
figurations. The register configuration of Table 1 shows
each bit name and the bit usage information for all regis-
ters. Note that all registers must be written after and no
earlier than 100μs after the device is powered up.
LSB
REG
NO
REGISTER READ/ REG
NAME WRITE ADDRESS
DATA BYTE
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
1
2
3
4
5
N-Divider
MSB
N-Divider
LSB
Charge
Pump
Not Used
Not Used
Write
Write
Write
Write
Write
0x00
0x01
0x02
0x03
0x04
X
N[7]
CPMP[1]
0
X
X
N[14]
N[6]
CPMP[0]
0
X
X
N[13]
N[5]
CPLIN[1]
0
X
X
N[12]
N[4]
CPLIN[0]
0
X
X
N[11]
N[3]
X
X
X
N[10]
N[2]
X
X
X
N[9]
N[1]
X
X
X
N[8]
N[0]
X
X
X
XTAL
6
Divider/
Write
0x05
XD[2]
XD[1]
XD[0]
R[4]
R[3]
R[2]
R[1]
R[0]
R-Divider
7
8
PLL
VCO
Write
Write
0x06
0x07
D24
VCO[4]
CPS
VCO[3]
ICP
VCO[2]
X
VCO[1]
X
VCO[0]
X
VAS
X
ADL
X
ADE
9
10
LPF
Control
Write
Write
0x08
0x09
LPF[7]
STBY
LPF[6]
X
LPF[5]
PWDN
0
LPF[4]
X
LPF[3]
BBG[3]
LPF[2] LPF[1] LPF[0]
BBG[2] BBG[1] BBG[0]
11
Shutdown
Write
0x0A
X
PLL
0
DIV
0
VCO
0
BB
0
RFMIX RFVGA
0 0
FE
0
12
Test
Write
0x0B
CPTST[2]
0
CPTST[1]
0
CPTST[0]
0
X
TURBO
1
LD LD LD
MUX[2] MUX[1] MUX[0]
0 0 0
13
Status
Byte-1
Read
0x0C
POR
VASA
VASE
LD
X
X
X
X
14
Status
Byte-2
Read
0x0D
VCOSBR[4] VCOSBR[3] VCOSBR[2] VCOSBR[1] VCOSBR[0] ADC[2] ADC[1] ADC[0]
0 = Set to “0” for factory-tested operation.
1 = Set to “1” for factory-tested operation.
X = Don’t care.
Table 2. N-Divider MSB Register
BIT NAME
X
N[14:8]
BIT LOCATION (0 = LSB)
7
6–0
DEFAULT
X
0000011
FUNCTION
Don’t care.
Sets the most significant bits of the PLL integer-divide number (N).
Default value is N = 950 decimal. N can range from 16 to 2175.
Table 3. N-Divider LSB Register
BIT NAME
N[7:0]
BIT LOCATION (0 = LSB)
7 –0
DEFAULT
10110110
FUNCTION
Sets the least significant bits of the PLL integer-divide number (N).
Default value is N = 950 decimal. N can range from 16 to 2175.
10
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