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参数资料
| 型号： | MAX2870ETJ+ |
| 厂商： | Maxim Integrated |
| 文件页数： | 4/24页 |
| 文件大小： | 0K |
| 描述： | RF FRACT INTR N SYNTH VCO 32TQFN |
| 标准包装： | 60 |
| 功能： | 小数、整数 N 频率合成器/VCO |
| 频率： | 23.5MHz ~ 6GHz |
| RF 型： | 通用 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 包装： | 管件 |
MAX2870
23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer/VCO
DIGITAL I/O CHARACTERISTICS
(V CC_ = +3V to +3.6V, V GND_ = 0V, T A = -40 N C to +85 N C. Typical values at V CC_ = 3.3V, T A = +25 N C.) (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SERIAL INTERFACE INPUTS (CLK, DATA, LE, CE, RFOUT_EN)
Input Logic-Level Low
Input Logic-Level High
V IL
V IH
1.5
0.4
V
V
Input Current
Input Capacitance
I IH /I IL
-1
1
+1
F A
pF
SERIAL INTERFACE OUTPUTS (MUX_OUT, LD)
Output Logic-Level Low
Output Logic-Level High
Output Current Level High
0.3mA sink current
0.3mA source current
V CC - 0.4
0.4
0.5
V
V
mA
SPI TIMING CHARACTERISTICS
(V CC_ = +3V to +3.6V, V GND_ = 0V, T A = -40 N C to +85 N C. Typical values at V CC_ = 3.3V, T A = +25 N C.) (Note 2)
PARAMETER
CLK Clock Period
SYMBOL
t CP
CONDITIONS
Guaranteed by SCL pulse-width
low and high
MIN
50
TYP
MAX
UNITS
ns
CLK Pulse-Width Low
CLK Pulse-Width High
LE Setup Time
LE Hold Time
LE Minimum Pulse-Width High
Data Setup Time
Data Hold Time
MUX_OUT Setup Time
MUX_OUT Hold Time
t CL
t CH
t LES
t LEH
t LEW
t DS
t DH
t MS
t MH
25
25
20
10
20
25
25
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 2: Production tested at T A = +25 N C. Cold and hot are guaranteed by design and characterization.
Note 3: f REFIN = 100MHz, phase detector frequency = 25MHz, RF output = 6000MHz.
Register setting: 00780000, 20400061, 20011242, F8010003, 608001FC, 80440005
Note 4: Measured single ended with 27nH to V CC_RF into 50 I load. Power measured with single output enabled. Unused output
has 27nH to V CC_RF with 50 I termination.
Note 5: VCO phase noise is measured open loop.
Note 6: Measured at 200kHz using a 50MHz Bliley NV108C19554 OCVCXO with 2MHz loop bandwidth. Register setting
801E0000, 8000FFF9, 80005FC2, 6C10000B, 638E80FC, 400005. EV kit loop filter: C13 = 1500pF, C14 = 33pF, R1 = 0?,
R2 = 1100?, R0 = 0?, C12 = open.
Note 7: 1/f noise contribution to the in-band phase noise is computed by using 1/fnoise + 10log(10kHz/f OFFSET ) +
20log(f RF /1GHz). Register setting: 803A0000,8000FFF9,81005F42,F4000013,6384803C,001500005
Note 8: f REFIN = 50MHz; f PFD = 25MHz; offset frequency = 10kHz; VCO frequency = 4227MHz, output divide-by-2 enabled.
RFOUT = 2113.5MHz; N = 169; loop BW = 40kHz, CP[3:0] = 1111; integer mode.
Note 9: f REFIN = 50MHz; f PFD = 50MHz; VCO frequency = 4400MHz, f RFOUT_ = 4400MHz; loop BW = 65kHz. Register setting:
002C0000, 200303E9, 80005642, 00000133, 638E82FC, 01400005. EV kit loop filter: C13 = 0.1μF, C14 = 0.012μF, R1 =
0?, R2 = 120?, R0 = 250?, C12 = 820pF.
Maxim Integrated
4
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