参数资料
型号: MAX3108EWA+T
厂商: Maxim Integrated Products
文件页数: 5/56页
文件大小: 0K
描述: IC UART
产品培训模块: Obsolescence Mitigation Program
标准包装: 2,500
系列: *
SPI/I2C UART with 128-Word FIFOs in WLP
MAX3108
13
Maxim Integrated
Bump Configuration
Bump Description
MAX3108
MISO/
SDA
CS/A0
IRQ
VCC
23
4
1
A
RST
SCLK/
SCL
MOSI/
A1
V18
B
LDOEN
N.C.
TOP VIEW
(BUMPS ON BOTTOM)
WLP
(2.1mm × 2.1mm)
GPIO0
VL
5
DGND
GPIO1
AGND
C
XOUT
SPI/I2C
GPIO3CTS
XIN
D
GPIO2
RTS
TX
RX
VEXT
E
+
BUMP
NAME
FUNCTION
A1
VCC
Analog Power Supply. VCC powers the PLL and internal LDO. Bypass VCC with a 0.1FF ceramic
capacitor to AGND.
A2
MISO/SDA
Serial-Data Output. When SPI/I2C is high, MISO/SDA functions as the SPI master input, slave output
(MISO). When SPI/I2C is low, MISO/SDA functions as the SDA, I2C serial-data input/output.
A3
CS/A0
Active-Low Chip-Select and Address 0 Input. When SPI/I2C is high, CS/A0 functions as the CS, SPI
active-low chip-select. When SPI/I2C is low, CS/A0 functions as the A0 I2C device address programming
input. Connect CS/A0 to DGND, VL, SCL, or SDA when SPI/I2C is low.
A4
IRQ
Active-Low Interrupt Open-Drain Output. IRQ is asserted when an interrupt is pending and during initial
power-up.
A5
VL
Digital Interface Power Supply. VL powers the internal logic-level translators for RST, IRQ, MOSI/A1, CS/A0,
SCLK/SCL, MISO/SDA, LDOEN, and SPI/I2C. Bypass VL with a 0.1FF ceramic capacitor to DGND.
B1
V18
Internal 1.8V LDO Output and 1.8V Power-Supply Input. Bypass V18 with a 1FF ceramic capacitor to
DGND.
B2
RST
Active-Low Reset Input. Drive RST low to force the UART into hardware reset mode. In hardware reset
mode, the internal PLL is shut down and there is no clock activity.
B3
SCLK/SCL
Serial-Clock Input. When SPI/I2C is high, SCLK/SCL functions as the SCLK SPI serial-clock input (up to
26MHz). When SPI/I2C is low, SCLK/SCL functions as the SCL, I2C serial-clock input (up to 1MHz in fast
mode plus).
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