参数资料
型号: MAX3108EWA+T
厂商: Maxim Integrated Products
文件页数: 7/56页
文件大小: 0K
描述: IC UART
产品培训模块: Obsolescence Mitigation Program
标准包装: 2,500
系列: *
SPI/I2C UART with 128-Word FIFOs in WLP
MAX3108
15
Maxim Integrated
Detailed Description
The MAX3108 universal asynchronous receiver-trans-
mitter (UART) bridges an SPI/MICROWIREK or I2C
microprocessor bus to an asynchronous serial-data
communication link. The MAX3108 contains an advanced
UART, a fractional baud-rate generator, and four GPIOs.
Eight-bit registers configure and monitor the MAX3108
and are accessed through SPI or I2C, selectable by an
external pin. The registers are organized by related func-
tion as shown in the Register Map section.
The host controller loads data into the Transmit Hold
register (THR) through the SPI or I2C interface. This data
is automatically pushed into the transmit first-in/first-out
(FIFO), formatted, and sent out at TX. The MAX3108
adds START, STOP, and parity bits to the data before
transmitting at the selected baud rate. The clock configu-
ration registers determine the baud rate, clock source,
and clock frequency prescaling.
The MAX3108 receiver detects a START bit as a high-
to-low transition on RX. An internal clock samples this
data at 16 times the baud rate. The received data is
automatically placed in the receive FIFO and can be
read out by the host microcontroller through the Receive
Hold register (RHR).
The MAX3108’s register set is compatible with the
MAX3107.
Register Set
The MAX3108 has a flat register structure without shadow
registers. The registers are 8 bits wide. The MAX3108
registers have some similarities to the 16C550 registers.
Receive and Transmit FIFOs
The UART’s receiver and transmitter each have a
128-word-deep FIFO, reducing the number of intervals
that the host processor needs to dedicate for high-
speed, high-volume data transfer to and from the device.
As the data rates of the asynchronous RX/TX interfaces
increase and get closer to those of the host controller’s
SPI/I2C data rates, UART management and flow-control
can make up a significant portion of the host’s activity.
By increasing FIFO size, the host is interrupted less often
and can use data block transfers to and from the FIFOs.
FIFO trigger levels can generate interrupts to the host
controller, signaling that programmed FIFO fill levels
have been reached. The transmitter and receiver trigger
levels are programmed through the FIFOTrgLvl register
with a resolution of eight FIFO locations. The receive
FIFO trigger signals to the host either that the receive
FIFO has a defined number of words waiting to be read
out in a block or that a known number of vacant FIFO
locations are available and ready to be filled. The trans-
mit FIFO trigger generates an interrupt when the transmit
FIFO fill level is above the programmed trigger level. The
host then knows to throttle data writing to the transmit
FIFO through THR.
The host can read out the number of words pres-
ent in each of the FIFOs through the TxFIFOLvl and
RxFIFOLvl registers.
The contents of the TxFIFO and RxFIFO are both cleared
when the MODE2[1]: FIFORst bit is set high.
Transmitter Operation
Figure 3 shows the structure of the transmitter with the
TxFIFO. The transmit FIFO can hold up to 128 words of
data that are added by writing to the THR register.
The current number of words in the TxFIFO can be
manually read out by the host controller through the
TxFIFOLvl register. The transmit FIFO fill level can be
MICROWIRE is a trademark of National Semiconductor Corp.
Figure 3. Transmit FIFO Signals
CURRENT FILL LEVEL
TRANSMITTER
TX
TRANSMIT FIFO
FIFOTrgLvl[3:0]
TRIGGER
ISR[4]
THR
DATA FROM SPI/I2C INTERFACE
128
3
2
1
LEVEL
TxFIFOLvl
EMPTY
ISR[5]
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