参数资料
| 型号： | MAX3108EWA+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 6/56页 |
| 文件大小： | 0K |
| 描述： | IC UART |
| 产品培训模块： | Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | * |
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SPI/I2C UART with 128-Word FIFOs in WLP
MAX3108
14
Maxim Integrated
Bump Description (continued)
BUMP
NAME
FUNCTION
B4
MOSI/A1
Serial-Data Input and Address 1 Input. When SPI/I2C is high, MOSI/A1 functions as the SPI master
output-slave input (MOSI). When SPI/I2C is low, MOSI/A1 functions as the A1 I2C device address
programming input. Connect MOSI/A1 to DGND, VL, SCL, or SDA when SPI/I2C is low.
B5
DGND
Digital Ground
C1
AGND
Analog Ground
C2
LDOEN
LDO Enable Input. Drive LDOEN high to enable the internal 1.8V LDO. Drive LDOEN low to disable the
internal LDO. Supply V18 with an external voltage source when LDOEN is low.
C3
N.C.
Not Connected. Internally not connected.
C4
GPIO0
General-Purpose Input/Output 0. GPIO0 is user-programmable as an input or output (push-pull or open
drain) or an external event-driven interrupt source. GPIO0 has a weak pulldown resistor to DGND when
configured as an input.
C5
GPIO1
General-Purpose Input/Output 1. GPIO1 is user programmable as an input or output (push-pull or open
drain) or an external event-driven interrupt source. GPIO1 has a weak pulldown resistor to DGND when
configured as an input.
D1
XIN
Crystal/Clock Input. When using an external crystal, connect one end of the crystal to XIN and the other
end to XOUT. When using an external clock source, drive XIN with the single-ended external clock.
D2
XOUT
Crystal Output. When using an external crystal, connect one end of the crystal to XOUT and the other
end to XIN. When using an external clock source, leave XOUT unconnected.
D3
SPI/I2C
SPI Selector Input or Active-Low I2C. Drive SPI/I2C low to enable I2C. Drive SPI/I2C high to enable SPI.
D4
GPIO3
General-Purpose Input/Output 3. GPIO3 is user-programmable as input or output (push-pull or open
drain) or an external event-driven interrupt source. GPIO3 has a weak pulldown resistor to DGND when
configured as an input.
D5
CTS
Active-Low Clear-to-Send Input. CTS is a flow-control status input.
E1
VEXT
Transceiver Interface Power Supply. VEXT powers the internal logic-level translators for RX, TX, RTS,
CTS, and GPIO_. Bypass VEXT with a 0.1FF ceramic capacitor to DGND.
E2
GPIO2
General-Purpose Input/Output 2. GPIO2 is user programmable as input or output (push-pull or open
drain) or an external event-driven interrupt source. GPIO2 has a weak pulldown resistor to DGND when
configured as an input.
E3
RTS
Active-Low Request-to-Send Output. RTS can be set high or low by programming the LCR register.
E4
TX
Serial Transmitting Data Output.
E5
RX
Serial Receiving Data Input. RX has an internal weak pullup resistor to VEXT.
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