参数资料
型号: MAX31782ETL+T
厂商: Maxim Integrated Products
文件页数: 16/20页
文件大小: 0K
描述: IC MICROCONTROLLER 40TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 3,000
系列: MAXQ®
应用: 系统管理
核心处理器: MAXQ20
程序存储器类型: 闪存(64 kB),ROM(8 kB)
RAM 容量: 1K x 16
接口: I²C,SM 总线
输入/输出数: 5
电源电压: 2.7 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 40-TQFN-EP(6x6)
其它名称: 90-31782+TTR
MAX31782
System Management Microcontroller
5
ELECTRICAL CHARACTERISTICS: JTAG INTERFACE
(VDD = 2.7V to 5.5V, TA = -40NC to +85NC, unless otherwise noted.) (Figure 2)
Note 1: All voltages are referenced to ground (VSS). Currents entering the IC are specified positive and currents exiting the IC are
negative.
Note 2: This value does not include current in SDA, SCL, and P6.0–P6.4.
Note 3: Guaranteed by design.
Note 4: ADCCLK = SYSCLK/16. This is following an initial startup time of approximately 80s.
Note 5: Base line accuracy of reference source + 0.25% introduced by the MAX31782.
Note 6: The voltage applied to the pins must not exceed their corresponding absolute maximum voltages.
Note 7: ADC has no missing codes.
Note 8: Minimum SCL frequency applies only when in I2C master mode.
Note 9: After this period, the first clock pulse can be generated.
Note 10: This device internally provides a hold time of at least 25ns for the SDA signal (referenced to the VIHMIN of the SCL signal)
to bridge the undefined region of the falling edge of SCL.
Note 11: CB—Total capacitance of one bus line in pF.
Note 12: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
Figure 1. I2C-Compatible Bus Timing Diagram
SCL
NOTE: TIMING IS REFERENCED TO VILMAX AND VIHMIN.
SDA
STOP
START
REPEATED
START
tBUF
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tHD:STA
tSP
tSU:STA
tHIGH
tR
tF
tLOW
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
JTAG Logic Reference
VREF
VDD/2
V
TCK High Time
tTH
1
F
s
TCK Low Time
tTL
1
F
s
TCK Low to TDO Output
tTLQ
0.125
F
s
TMS, TDI Input Setup to TCK
High
tDVTH
0.30
F
s
TMS, TDI Input Hold after TCK
High
tTHDX
0.25
F
s
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