参数资料
型号: MAX31782ETL+T
厂商: Maxim Integrated Products
文件页数: 8/20页
文件大小: 0K
描述: IC MICROCONTROLLER 40TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 3,000
系列: MAXQ®
应用: 系统管理
核心处理器: MAXQ20
程序存储器类型: 闪存(64 kB),ROM(8 kB)
RAM 容量: 1K x 16
接口: I²C,SM 总线
输入/输出数: 5
电源电压: 2.7 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 40-TQFN-EP(6x6)
其它名称: 90-31782+TTR
MAX31782
System Management Microcontroller
16
Tachometer Inputs
The device provides six pins for reading fan tachometer
pulses. Each TACH.n pin functions independently and is
associated with three SFRs: TACHCNn (the control reg-
ister), TACHVn (the timer value register), and TACHRn
(the timer capture register), where n = 0–5 is the channel
number.
There is an internal timer for each TACH.n pin. The clock
for the TACH.n timer is derived from the system clock
with a division ratio defined by TACHCNn. The TACH.n
timer, when initially enabled, begins counting up from the
TACHVn value and upon overflow subsequently contin-
ues counting from 0000h to the FFFFh overflow, i.e., rolls
over from FFFFh to 0000h if left enabled and running.
If the capture function is enabled by configuring the
TACHCNn register, a 1-to-0 transition on the prescaled
tachometer pulses causes the value in the TACHVn reg-
ister to be transferred into the TACHRn register and set
the external trigger flag. Upon capture, TACHVn reloads
0000h and continues counting. The user can calculate
the tachometer pulse period and the fan speed by read-
ing the TACHRn register.
When the tachometer input functionality of a TACH.n
pin is disabled, that pin can be used as a GPIO. When
used as GPIO pins, TACH.n pins are accessed as port
2 and through three SFRs: PO2, PI2, and PD2. Each
TACH.n pin can be independently configured, and can
be defined as an input with weak pullup, an input without
pullup, or an output.
I2C-Compatible Interface Modules
The device provides two independent I2C-compatible
interfaces; one is a master and the other is a slave.
I2C-Compatible Master Interface
The device features an internal I2C-comaptible mas-
ter interface for communication with a wide variety of
external I2C devices. The I2C-compatible master bus is
a bidirectional bus using two bus lines, the serial-data
line (MSDA) and the serial-clock line (MSCL). For the
I2C-compatible master, the device has ownership of the
I2C bus, and drives the clock and generates the START
and STOP signals. This allows the device to send data
to a slave or receive data from a slave as required. Both
the MSDA and MSCL lines must be driven as open-drain
outputs. External pullup resistors are required to pull the
lines to a logic-high state.
When the I2C-compatible master interface is disabled,
MSDA and MSCL can be used as GPIO pins. When used
as GPIO pins, MSDA and MSCL can be used as pins
P2.7 and P2.6, respectively, and are accessed through
three SFRs: PO2, PI2, and PD2. Because these pins are
open drain, external pullups are required to realize a
logic-high.
I2C-Compatible Slave Interface
The device also features an internal I2C-comaptible slave
interface for communication with a host. Furthermore, the
device can be in-system programmed (bootloaded)
through the I2C-compatible slave interface. For the
I2C-compatible slave interface, the device relies on an
externally generated clock to drive SCL and responds
to data and commands only when requested by the I2C
master device.
SMBus Timeout
Both the I2C-compatible master and slave interfaces can
work in SMBus-compatible mode for communication with
other SMBus devices. To achieve this, a 30ms timer has
been implemented on the I2C-compatible slave interface
to make the interface SMBus compatible. The purpose
of this timer is to issue a timeout interrupt and thus the
firmware can reset the I2C-compatible slave interface
when the SCL is held low for longer than 30ms. The timer
only starts when none of the following conditions is true:
TheI2C-compatible slave interface is in the idle state
and there is no communication on the bus.
TheI2C-compatible slave interface is not working in
SMBus-compatible mode.
TheSCLlogiclevelishigh.
TheI2C-compatible slave interface is disabled.
When a timeout occurs, the timeout bit is set and an
interrupt is generated, if enabled. If a timeout interrupt is
generated, the firmware disables and reenables the I2C-
compatible slave interface. After this process, the SCL
and SDA pins are set to high impedance. All the relevant
I2C slave SFRs should be reloaded by firmware.
Analog-to-Digital Converter (ADC)
The device contains a 12-bit analog-to-digital converter
(ADC) with a 7-input mux (Figure 5). The mux selects the
ADC input from six external channels and one internal
channel. The six external channels can operate in fully
differential voltage mode or in single-ended voltage
mode. In addition, any of the six external channels can
be configured to measure the temperature of an external
diode. The internal channel is used exclusively to mea-
sure the die temperature. The ADC is controlled by SFR
registers.
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