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参数资料
| 型号： | MAX3886ETN+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 3/17页 |
| 文件大小： | 0K |
| 描述： | IC MULTIRATE CDR SER/DES56-TQFN |
| 标准包装： | 2,500 |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 是 |
| 主要目的： | 光纤网络终端（ONT）应用，千兆位无源光纤网络（GPON），宽带无源光纤网络（BPON） |
| 输入： | CML，LVDS，LVPECL |
| 输出： | CML，LVDS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 7:6 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 622MHz，2488Mbps |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-WFQFN 裸露焊盘 |
| 供应商设备封装： | 56-TQFN-EP（8x8） |
| 包装： | 带卷 (TR) |
Burst-Enable Signal Processing
To minimize PON overhead, it is important that the laser
driver burst-enable (BEN) signal correspond accurately
with the beginning of the serial data burst. This is sup-
ported in the MAX3886 by the BENI LVDS input and
associated signal path. The LVDS burst-enable signal
from the MAC layer IC is passed through the same FIFO
as the parallel data and output on the BENO CML out-
put, which ensures that the laser driver’s burst enable
matches the beginning of the associated serial MSB. If
FRST or FERR are high, the BENO output is forced low
to prevent the laser driver from transmitting erroneous
data. The parallel data setup and hold timing require-
ments also apply to the burst-enable signal.
Lock Detector Output
The lock detector operates by comparing a divided-
down version of the VCO output to the reference clock.
The LOCK output pin indicates lock (high) when the fre-
quency difference between the reference clock and the
CDR VCO is less than 250ppm, within the “pullin” range
of the PLL. The LOCK output indicates out-of-lock (low)
when the frequency difference between the reference
clock and the CDR VCO becomes more than 500ppm.
When valid input data is present, this provides a stable
lock indication.
At power-up, the CDR takes approximately 50ms (if
valid NRZ data is present) for initial acquisition while
the internal reference oscillator, the PLL, and the fre-
quency detector reach their operating conditions.
During this startup period, the LOCK status output may
provide false indication of a lock condition. Once the
PLL and frequency detector are initialized, the nominal
time for reacquisition of an NRZ input is 2ms.
When valid NRZ input data is not present, the lock
detector may produce a chattering LOCK indicator out-
put while the PLL searches for the input frequency. If
needed, an external digital filter can be used to mask
this chattering.
Table 1. Lock Detector Output
Control Input Summary
Table 2 summarizes the clock and data rates as con-
trolled by MVCO, MSYM, and MDDR.
MAX3886
Multirate CDR with Integrated Serializer/Deserializer
for GPON and BPON ONT Applications
______________________________________________________________________________________
11
CDR INPUT
LOCK OUTPUT
Valid NRZ data
1
No CDR input
0/1 (chatter)
Table 2. Clock and Data Rate Controls
Rx
Tx
MVCO
MSYM
MDDR
SDI RATE
(Mbps)
PDO RATE
(Mbps)
PCKO
(MHz)
SDO RATE
(Mbps)
PDI RATE
(Mbps)
PCKI
(MHz)
RCKO
(MHz)
0
622
155
39
0
1
622
155
78
155
39
0
1
0
622
155
622
155
0
1
622
155
78
622
155
Open
0
1244
311
622
155
Open
0
1
1244
311
155
622
155
Open
1
0
1244
311
1244
311
Open
1
1244
311
155
1244
311
1
0
2488
622
1244
311
1
0
1
2488
622
311
1244
311
1
0
2488
622
2488
622
1
2488
622
311
2488
622
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