参数资料
型号: MAX3946ETG+T
厂商: Maxim Integrated
文件页数: 10/29页
文件大小: 0K
描述: IC LASER DVR SFP 11.3GBPS 24TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 激光二极管驱动器
数据速率: 11.3Gbps
通道数: 1
电源电压: 2.85 V ~ 3.63 V
电流 - 电源: 68mA
电流 - 调制: 80mA
电流 - 偏置: 80mA
工作温度: -40°C ~ 85°C
封装/外壳: 24-WFQFN 裸露焊盘
供应商设备封装: 24-TQFN-EP(4x4)
包装: 带卷 (TR)
安装类型: 表面贴装
1Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
Pin Configuration
TOP VIEW
18
17
16
15
14
13
V EET 19
V CC 20
TIN+ 21
12
11
10
V CCT
TOUT+
TOUT+
TIN- 22
MAX3946
9
TOUT-
V CC 23
V EET 24
+
*EP
8
7
TOUT-
V CCT
1
2
3
4
5
6
THIN QFN
(4mm × 4mm)
*EXPOSED PAD CONNECTED TO GROUND.
Pin Description
PIN
1, 15
2
3
4
5
6, 7, 12, 13
8, 9
10, 11
14
16
17
NAME
V CCD
DISABLE
FAULT
BMAX
BMON
V CCT
TOUT-
TOUT+
BIAS
CSEL
SDA
FUNCTION
Power Supply. Provides supply voltage to the digital block.
Disable Input, CMOS. Set to logic-low for normal operation. Logic-high or open disables both the
modulation current and the bias current. Internally pulled up by a 7.5k I resistor to V CCD .
Fault Output, Open Drain. Logic-high indicates a fault condition. FAULT remains high even after the
fault condition has been removed. A logic-low occurs when the fault condition has been removed and
the fault latch has been cleared by toggling the DISABLE pin. FAULT should be pulled up to V CC by
a 4.7k I to 10k I resistor.
Analog Laser Bias-Current Limit. A resistive voltage-divider connected among BMON, BMAX, and
ground sets the maximum allowed laser bias current limit. The voltage at BMAX is internally com-
pared to 1.2V bandgap reference voltage.
Bias Current-Monitor Output. Current out of this pin develops a ground-referenced voltage across
external resistor(s) that is proportional to the laser bias current. The current sourced by this pin is
typically 1/100th the BIAS pin current.
Power Supply. Provides supply voltage to the output block.
Inverted Modulation Current Output. Internally pulled up by a 25 I resistor to V CCT .
Noninverted Modulation Current Output. Internally pulled up by a 25 I resistor to V CCT .
Laser Bias Current Connection. This pin requires a 0.1μF capacitor to V EET for proper operation.
Chip-Select Input, CMOS. Setting CSEL to logic-high starts a cycle. Setting CSEL to logic-low ends
the cycle and resets the control state machine. Internally pulled down by a 75k I resistor to V EET .
Serial-Data Bidirectional Input, CMOS. Open-drain output. This pin has a 75k I internal pullup, but it
requires an external 4.7k I to 10k I pullup resistor. (Data line-collision protection is implemented.)
10
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