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参数资料
| 型号： | MAX4940BETN+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 9/18页 |
| 文件大小： | 0K |
| 描述： | IC DGTL PULSER HI-VOLT 56TQFN |
| 标准包装： | 2,500 |
| 应用： | 医疗用超声波成像，声纳 |
| 电源电压： | 2.37 V ~ 6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
Dual/Quad, Unipolar/Bipolar,
High-Voltage Digital Pulsers
Pin Description (continued)
PIN
26, 45
28
30, 41
31, 40
32, 39
33
35, 36
38
43
46
47
48
49
50
51
52
53
56
—
NAME
V PP1
OUT1B
V NN1
V NN2
N.C.
OUT2B
V PP2
OUT2A
OUT1A
C GP1A
C GN1A
C GN2A
C GP2A
C DP2A
C DN2A
C DN1A
C DP1A
V DD
EP
FUNCTION
Channel 1A, 1B High-Side Positive Supply Voltage Input. Bypass V PP1 to GND with a 0.1 F F
capacitor as close as possible to the device.
Channel 1B Output
Channel 1A, 1B Low-Side Negative Supply Voltage Input. Bypass V NN1 to GND with a 0.1 F F
capacitor as close as possible to the device.
Channel 2A, 2B Low-Side Negative Supply Voltage Input. Bypass V NN2 to GND with a 0.1 F F
capacitor as close as possible to the device.
No Connection. Not connected internally.
Channel 2B Output
Channel 2A, 2B High-Side Positive Supply Voltage Input. Bypass V PP2 to GND with a 0.1 F F
capacitor as close as possible to the device.
Channel 2A Output
Channel 1A Output
Channel 1A High-Side Gate Input. Connect a 3.3nF capacitor between C DP1A and C GP1A as close
as possible to the device.
Channel 1A Low-Side Gate Input. Connect a 3.3nF capacitor between C DN1A and C GN1A as close
as possible to the device.
Channel 2A Low-Side Gate Input. Connect a 3.3nF capacitor between C DN2A and C GN2A as close
as possible to the device.
Channel 2A High-Side Gate Input. Connect a 3.3nF capacitor between C DP2A and C GP2A as close
as possible to the device.
Channel 2A High-Side Driver Output. Connect a 3.3nF capacitor between C DP2A and C GP2A as
close as possible to the device.
Channel 2A Low-Side Driver Output. Connect a 3.3nF capacitor between C DN2A and C GN2A as
close as possible to the device.
Channel 1A Low-Side Driver Output. Connect a 3.3nF capacitor between C DN1A and C GN1A as
close as possible to the device.
Channel 1A High-Side Driver Output. Connect a 3.3nF capacitor between C DP1A and C GP1A as
close as possible to the device.
Logic-Supply Voltage Input. Bypass V DD to GND with a 0.1 F F capacitor as close as possible to the
device.
Exposed Pad. EP must be connected to V NN1 .
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