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参数资料
| 型号： | MAX5061EUE+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 17/31页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 16TSSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.5MHz |
| 占空比： | 90% |
| 电源电压： | 4.75 V ~ 28 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 包装： | 带卷 (TR) |
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0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
Internal Oscillator
The internal oscillator generates a clock with the fre-
quency proportional to the inverse of R T . The oscillator
frequency is adjustable from 125kHz to 1.5MHz with
better than 8% accuracy using a single resistor con-
nected from RT/SYNC to SGND (MAX5060) and from
RT/SYNC/EN to SGND (MAX5061). The frequency accu-
racy avoids the over-design, size, and cost of passive
filter components like inductors and capacitors. Use the
following equation to calculate the oscillator frequency:
for 120k ? ≤ R T ≤ 500k ? :
The oscillator also generates a 2V P-P voltage-ramp sig-
nal for the PWM comparator and a 180° out-of-phase
clock signal for CLKOUT (MAX5060) to drive a second
DC-DC converter out-of-phase.
Synchronization
The MAX5060/MAX5061 can be easily synchronized by
connecting an external clock to RT/SYNC (MAX5060) or
RT/SYNC/EN (MAX5061). If an external clock is pre-
sent, then the internal oscillator is disabled and the
external clock is used to run the MAX5060/MAX5061. If
the external clock is removed, the absence of clock for
R T =
for 40k ? ≤ R T ≤ 120k ? :
R T =
6 . 25 × 10 10
f SW
6 . 40 × 10 10
f SW
32μs is detected and the circuit starts switching from
the internal oscillator. Pulling RT/SYNC on the MAX5060
or RT/SYNC/EN on the MAX5061 to ground for at least
50μs disables the converter.
Use an open-collector transistor to synchronize the
MAX5060/MAX5061 with the external system clock (see
Figures 1 and 2).
R CF
C CF
CSN
CSP
CLP
C CFF
CA
R F *
V IN
SENSE+
SENSE-
DIFF
AMP
R IN *
VEA
CEA
CPWM
DRIVE
I L
R S
V OUT
V REF + V CM
*R F AND R IN ARE EXTERNAL.
Figure 5. MAX5060 Control Loop
MAX5060
C OUT
LOAD
______________________________________________________________________________________
17
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