参数资料
型号: MAX5061EUE+T
厂商: Maxim Integrated Products
文件页数: 25/31页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 16TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 电流模式
输出数: 1
频率 - 最大: 1.5MHz
占空比: 90%
电源电压: 4.75 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 带卷 (TR)
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
( I DC + I PK + I )
I RMS ? HI =
DC PK ×
× I
( ? V ESR )
ESR IN =
? I OUT +
? ? I L ?
?
2 ?
I OUT × D ( 1 ? D )
C IN =
2 2 D
3
where D = V OUT /V IN , I DC = (I OUT - ? I L /2) and I PK =
(I OUT + ? I L /2).
PD MOS ? LO = ( Q G × V DD × f SW ) +
?
? V Q × f SW
where I OUT is the output current of the converter.
? 2 × C
(
× V 2 × f
?
? + 1 . 4 R DS ( ON ) × I RMS ? LO
?
?
?
( I DC + I PK + I
)
2 2 ( 1 ? D )
I RMS ? LO = DC × I PK ×
3
OSS IN SW 2
3
)
For example, at V OUT = 1.8V, the ESR and input capac-
itance are calculated for the input peak-to-peak ripple
of 100mV or less yielding an ESR and capacitance
value of 1.25m ? and 110μF.
Output Capacitors
The worst-case peak-to-peak and capacitor RMS ripple
? V OESR
? I L
C OUT =
where C OSS is the MOSFET drain-to-source capaci-
tance.
For example, from the typical specifications in the
Applications Information section with V OUT = 1.8V, the
high-side and low-side MOSFET RMS currents are 7.8A
and 18.5A, respectively for 20A. Ensure that the ther-
mal impedance of the MOSFET package keeps the
junction temperature at least +25°C below the absolute
maximum rating. Use the following equation to calcu-
late maximum junction temperature:
T J = (PD MOS x θ JA ) + T A
where θ JA and T A are the junction-to-ambient thermal
impedance and ambient temperature, respectively.
Input Capacitors
The discontinuous input-current waveform of the buck
converter causes large ripple currents in the input capac-
itor. The switching frequency, peak inductor current, and
the allowable peak-to-peak voltage ripple reflected back
to the source dictate the capacitance requirement.
Increasing switching frequency or paralleling multiple out-
of-phase converters lowers the peak-to-average current
ratio, yielding a lower input capacitance requirement for
the same load current.
The input ripple is comprised of ? V Q (caused by the
capacitor discharge) and ? V ESR (caused by the ESR of
the capacitor). Use low-ESR ceramic capacitors with
high-ripple-current capability at the input. Assume the
contributions from the ESR and capacitor discharge are
equal to 30% and 70%, respectively. Calculate the input
capacitance and ESR required for a specified ripple
using the following equation:
current, the allowable peak-to-peak output ripple volt-
age, and the maximum deviation of the output voltage
during step loads determine the capacitance and the
ESR requirements for the output capacitors.
In buck converter design, the output-current waveform
is continuous and this reduces peak-to-peak ripple cur-
rent in the output capacitor equal to the inductor ripple
current. Calculate the capacitance, the ESR of the out-
put capacitor, and the RMS ripple current rating of the
output capacitor based on the following equations.
ESR OUT =
? I L
8 × ? V OQ × f SW
where ? V OESR and ? V OQ are the output-ripple contri-
butions due to ESR and the discharge of output capaci-
tor, respectively.
In the dynamic load environment, the allowable devia-
tion of output voltage during the fast transient load dic-
tates the output capacitance and ESR. The output
capacitors supply the load step until the controller
responds with a greater duty cycle. The response time
(t RESPONSE ) depends on the closed-loop bandwidth of
the converter. The resistive drop across the capacitor
ESR and capacitor discharge causes a voltage drop
during a step load. Use a combination of SP polymer
and ceramic capacitors for better transient load and
ripple/noise performance.
______________________________________________________________________________________
25
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