参数资料
型号: MAX5065EAI+
厂商: Maxim Integrated Products
文件页数: 10/32页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 28-SSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 46
PWM 型: 电流模式
输出数: 1
频率 - 最大: 1MHz
占空比: 90%
电源电压: 4.75 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 28-SSOP(0.209",5.30mm 宽)
包装: 管件
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
Pin Description
PIN
MAX5065 MAX5067
NAME
FUNCTION
1, 13
2, 14
39, 16
40, 17
CSP2,
CSP1
CSN2,
CSN1
Current-Sense Differential Amplifier Positive Inputs. Sense the inductor current. The differential
voltage between CSP_ and CSN_ is amplified internally by the current-sense amplifier gain of
18.
Current-Sense Differential Amplifier Negative Inputs. Together with CSP_, sense the inductor
current.
Phase-Shift Setting Input. Connect PHASE to V CC for 120 ° , leave PHASE unconnected for 90 ° ,
3
41
PHASE
or connect PHASE to SGND for 60 ° of phase shift between the rising edge of CLKOUT and
CLKIN/DH1.
4
5, 7
6
42
43, 7
5, 20, 35
PLLCMP
CLP2,
CLP1
SGND
External Loop-Compensation Input. Connect compensation network for the phase-locked loop
(see the Phase-Locked Loop section).
Current-Error Amplifier Outputs. Compensate the current loop by connecting an RC network to
ground.
Signal Ground. Ground connection for the internal control circuitry.
Differential Output-Voltage-Sensing Positive Input. Used to sense a remote load. The MAX5065
8
10
SENSE+
and MAX5067 regulate the difference between SENSE+ and SENSE- according to the factory
preset reference voltage of +0.6V and +0.8V, respectively.
9
10
11
11
12
13
SENSE-
DIFF
EAN
Differential Output Voltage-Sensing Negative Input. Used to sense a remote load. Connect
SENSE- to V OUT- or PGND at the load.
Differential Remote-Sense Amplifier Output. DIFF is the output of a precision unity-gain
amplifier.
Voltage-Error Amplifier Inverting Input. Receives a signal from the output of the differential
remote-sense amplifier. Referenced to SGND.
Voltage-Error Amplifier Output. Connect to the external gain-setting feedback resistor. The
12
14
EAOUT
external error amplifier gain-setting resistors determine the amount of adaptive voltage
positioning.
15
16, 26
17, 25
18, 24
19
22, 34
23, 32
24, 31
EN
BST1,
BST2
DH1,
DH2
LX1, LX2
Output Enable. A logic-low shuts down the power drivers. EN has an internal 5μA pullup
current.
Boost Flying-Capacitor Connection. Reservoir capacitor connection for the high-side FET driver
supply. Connect a 0.47μF ceramic capacitor between BST_ and LX_.
High-Side Gate-Driver Outputs. Drive the gate of the high-side MOSFET.
Inductor Connection. Source connection for the high-side MOSFETs. Also serve as the return
terminal for the high-side driver.
19, 23
25, 30
DL1, DL2 Low-Side Gate-Driver Outputs. Synchronous MOSFET gate drivers for the two phases.
20
27
V CC
Internal +5V Regulator Output. V CC is derived internally from the IN voltage. Bypass to SGND
with 4.7μF and 0.1μF ceramic capacitors in parallel.
Supply Voltage Connection. Connect IN to V CC for a +5V system. Connect the unregulated
21
28
IN
power source to IN through an RC lowpass filter comprised of a 2.2 ? resistor and a 0.1μF
ceramic capacitor.
22
29
PGND
Power Ground. Connect the V CC bypass capacitors, input capacitors, output capacitors, and
low-side synchronous MOSFET source to PGND.
10
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