参数资料
型号: MAX5065EAI+
厂商: Maxim Integrated Products
文件页数: 11/32页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 28-SSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 46
PWM 型: 电流模式
输出数: 1
频率 - 最大: 1MHz
占空比: 90%
电源电压: 4.75 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 28-SSOP(0.209",5.30mm 宽)
包装: 管件
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
Pin Description (continued)
PIN
MAX5065 MAX5067
NAME
FUNCTION
27
36
CLKOUT
Oscillator Output. CLKOUT is phase-shifted from CLKIN by the amount determined by the
PHASE input. Use CLKOUT to parallel additional MAX5065/MAX5067s.
CMOS Logic Clock Input. Drive CLKIN with a frequency range between 125kHz and 600kHz or
28
38
CLKIN
connect to V CC or SGND. Connect CLKIN to SGND to set the internal oscillator to 250kHz or
connect to V CC to set the internal oscillator to 500kHz. CLKIN has an internal 5μA pulldown
current.
Overvoltage Protection Circuit Input. Connect OVPIN to the center of the resistive-divider
6
OVPIN
between V OUT and GND. When OVPIN exceeds +0.8V with respect to SGND, OVPOUT latches
DH_ low and DL_ high. Toggle EN low to high or recycle the power to reset the latch.
8
OVPOUT
Overvoltage Protection Output. Use the OVPOUT active-high, push-pull output to trigger a
safety device such as an SCR.
Power-Good Output. The open-drain, active-low PGOOD output goes low when the output
9
PGOOD
voltage falls out of regulation or a phase failure is detected. The power-good window-
comparator thresholds are +8% and -10% of the output voltage. Forcing EN low also forces
PGOOD low.
1, 2, 3, 4,
15, 18,
21, 33,
N.C.
No Connection. Not internally connected.
37, 44
Supply Voltage for Low-Side and High-Side Drivers. V CC powers V DD . Connect a parallel
26
V DD
combination of 0.1μF and 1μF ceramic capacitors to PGND and a 1 ? resistor to V CC to filter
out the high peak currents of the driver from the internal circuitry.
Detailed Description
The MAX5065/MAX5067 average-current-mode PWM
controllers drive two out-of-phase buck converter chan-
nels. Average-current-mode control improves current
sharing between the channels while minimizing compo-
nent derating and size. Parallel multiple MAX5065/
MAX5067 regulators to increase the output current
capacity. For maximum ripple rejection at the input, set
the phase shift between phases to 90 ° for two paral-
leled converters, or 60 ° for three paralleled converters.
Paralleling the MAX5065/MAX5067s improves design
flexibility in applications requiring upgrades (higher
load).
Dual-phase converters with an out-of-phase locking
arrangement reduce the input and output capacitor
ripple current, effectively multiplying the switching fre-
quency by the number of phases. Each phase of the
MAX5065/MAX5067 consists of an inner average cur-
rent loop controlled by a common outer-loop voltage-
error amplifier (VEA). The combined action of the two
+3.3V (MAX5065) and +0.8V to +3.3V (MAX5067) using
a resistive-divider at SENSE+ and SENSE-.
V IN , V CC , V DD
The MAX5065/MAX5067 accept a wide input voltage
range of +4.75V to +5.5V or +8V to +28V. All internal
control circuitry operates from an internally regulated
nominal voltage of +5V (V CC ). For input voltages of +8V
or greater, the internal V CC regulator steps the voltage
down to +5V. The V CC output voltage regulates to +5V
while sourcing up to 80mA. Bypass V CC to SGND with
4.7μF and 0.1μF low-ESR ceramic capacitors for high-
frequency noise rejection and stable operation (Figures
1, 2, and 3).
Calculate power dissipation in the MAX5065/MAX5067
as a product of the input voltage and the total V CC reg-
ulator output current (I CC ). I CC includes quiescent cur-
rent (I Q ) and gate-drive current (I DD ):
P D = V IN x I CC (1)
inner current loops and the outer voltage loop corrects
the output voltage errors and forces the phase currents
to be equal. Program the output voltage from +0.6V to
I CC = I Q + f SW x (Q G1 + Q G2 + Q G3 + Q G4 )
(2)
______________________________________________________________________________________
11
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