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参数资料
| 型号： | MAX5065EAI+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 20/32页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 28-SSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 46 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 90% |
| 电源电压： | 4.75 V ~ 28 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-SSOP（0.209"，5.30mm 宽） |
| 包装： | 管件 |
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Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
compensation provides a zero defined by 1 / [R4 x
V CNTR + ? V OUT /2
V CNTR
V CNTR - ? V OUT /2
(C31 + C32)] and a pole defined by 1 / (R4 x C32). Use
the following typical values for compensating the PLL:
R4 = 7.5k ? , C31 = 4.7nF, C32 = 470pF. If changing the
PLL frequency, expect a finite locking time of approxi-
mately 200μs.
The MAX5065/MAX5067 require compensation on
PLLCMP even when operating from the internal oscilla-
tor. The device requires an active PLL in order to gen-
NO LOAD
1/2 LOAD
FULL LOAD
erate the proper internal PWM clocks.
LOAD (A)
Figure 6. Defining the Voltage-Positioning Window
or allows for the use of higher ESR capacitors.
Voltage positioning may require the output to regulate
away from a center value. Define the center value as the
voltage where the output drops ( ? V OUT /2) at one half the
maximum output current (Figure 6).
Set the voltage-positioning window ( ? V OUT ) using the
resistive feedback of the VEA. Use the following equa-
tions to calculate the voltage-positioning window for the
MAX5065/MAX5067:
MOSFET Gate Drivers (DH_, DL_)
The high-side (DH_) and low-side (DL_) drivers drive
the gates of external N-channel MOSFETs (Figures 1, 2,
and 3). The drivers ’ high-peak sink and source current
capability provides ample drive for the fast rise and fall
times of the switching MOSFETs. Faster rise and fall
times result in reduced cross-conduction losses. For
modern CPU voltage-regulating module applications
where the duty cycle is less than 50%, choose high-
side MOSFETs (Q1 and Q3) with a moderate R DS(ON)
and a very low gate charge. Choose low-side
MOSFETs (Q2 and Q4) with very low R DS(ON) and
moderate gate charge.
The driver block also includes a logic circuit that provides
? V OUT = OUT IN × H L
I × R R + R
2 × G C × R F R L
(6)
an adaptive nonoverlap time to prevent shoot-through
currents during transition. The typical nonoverlap time is
60ns between the high-side and low-side MOSFETs.
BST_
G C =
0.05
R S
(7)
The MAX5067 uses V DD to power the low- and high-
side MOSFET drivers. The high-side drivers derive their
power through a bootstrap capacitor and V DD supplies
power internally to the low-side drivers. Connect a
where R IN and R F are the input and feedback resistors of
the VEA, G C is the current-loop transconductance, and
R S is the current-sense resistor.
Phase-Locked Loop: Operation and
Compensation
The PLL synchronizes the internal oscillator to the
external frequency source when driving CLKIN.
Connecting CLKIN to V CC or SGND forces the PWM
frequency to default to the internal oscillator frequency
of 500kHz or 250kHz, respectively. The PLL uses a
conventional architecture consisting of a phase detec-
tor and a charge pump capable of providing 20μA of
output current. Connect an external series combination
capacitor (C31) and resistor (R4) and a parallel capaci-
tor (C32) from PLLCMP to SGND to provide frequency
compensation for the PLL (Figure 1). The pole-zero pair
0.47μF low-ESR ceramic capacitor between BST_ and
LX_. Bypass V CC to SGND with 4.7μF and 0.1μF low-
ESR ceramic capacitors in parallel. Reduce the PC
board area formed by these capacitors, the rectifier
diodes between V CC and the boost capacitor, the
MAX5065/MAX5067, and the switching MOSFETs.
Overload Conditions
Average-current-mode control has the ability to limit the
average current sourced by the converter during a fault
condition. When a fault condition occurs, the VEA out-
put clamps to +0.9V with respect to the common-mode
voltage (V CM = +0.6V) and is compared with the output
of the current-sense amplifiers (CA1 and CA2) (see
Figure 4). The current-sense amplifier ’ s gain of 18 limits
the maximum current in the inductor or sense resistor to
I LIMIT = 50mV/R S .
20
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX5065EAI+ | 功能描述:电流型 PWM 控制器 Dual-Phase .6-3.3V Parallelable Average RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| MAX5065EAI+T | 功能描述:电流型 PWM 控制器 Dual-Phase .6-3.3V Parallelable Average RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| MAX5065EAI-T | 功能描述:电流型 PWM 控制器 Dual-Phase .6-3.3V Parallelable Average RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| MAX5065EVKIT | 功能描述:电源管理IC开发工具 MAX5065 Eval Kit RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
| MAX5066 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications |
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