参数资料
型号: MAX5067ETH+T
厂商: Maxim Integrated Products
文件页数: 18/32页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 44-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 电流模式
输出数: 1
频率 - 最大: 1MHz
占空比: 90%
电源电压: 4.75 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 44-WFQFN 裸露焊盘
包装: 带卷 (TR)
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
inductor with a saturation current specification greater
than the average current limit (48mV). Proper inductor
selection ensures that only extreme conditions trip the
peak-current comparator, such as a cracked output
inductor. The 112mV voltage threshold for triggering
the peak-current limit is twice the full-scale average
current-limit voltage threshold. The peak-current com-
parator has a delay of only 260ns.
Current-Error Amplifier
Each phase of the MAX5065/MAX5067 has a dedicated
transconductance current-error amplifier (CEA_) with a
typical g m of 550μS and 320μA output sink and source
current capability. The current-error amplifier outputs,
CLP1 and CLP2, serve as the inverting input to the
PWM comparator. CLP1 and CLP2 are externally
accessible to provide frequency compensation for the
inner current loops (Figure 4). Compensate CEA_ so
the inductor current down slope, which becomes the
R CF
up slope to the inverting input of the PWM comparator,
is less than the slope of the internally generated voltage
ramp (see the Compensation section).
PWM Comparator and R-S Flip-Flop
The PWM comparator (CPWM) sets the duty cycle for
each cycle by comparing the output of the current-error
amplifier to a 2V P-P ramp. At the start of each clock
cycle, an R-S flip-flop resets and the high-side driver
(DH_) turns on. The comparator sets the flip-flop as
soon as the ramp voltage exceeds the CLP_ voltage,
thus terminating the ON cycle (Figure 5).
Differential Amplifier
The differential amplifier (DIFF AMP) facilitates output
voltage remote sensing at the load (Figure 4). It pro-
vides true differential output voltage sensing while
rejecting the common-mode voltage errors due to high-
current ground paths. Sensing the output voltage
C CF
C CFF
MAX5065/
MAX5067
CA1
V IN
SENSE+
DIFF
R IN *
R F *
CEA1
CPWM1
DRIVE 1
I PHASE1
R S
AMP
SENSE-
VEA
V IN
V OUT
V REF
CEA2
CPWM2
DRIVE 2
I PHASE2
R S
C OUT
LOAD
CA2
*R F AND R IN ARE EXTERNAL.
Figure 4. MAX5065/MAX5067 Control Loop
R CF
C CCF
C CF
18
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