参数资料
型号: MAX5067ETH+T
厂商: Maxim Integrated Products
文件页数: 28/32页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 44-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 电流模式
输出数: 1
频率 - 最大: 1MHz
占空比: 90%
电源电压: 4.75 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 44-WFQFN 裸露焊盘
包装: 带卷 (TR)
Dual-Phase, +0.6V to +3.3V Output Parallelable,
Average-Current-Mode Controllers
The allowable deviation of the output voltage during the
fast transient load dictates the output capacitance and
ESR. The output capacitors supply the load step until
Calculate the maximum reverse current based on V CLR ,
the reverse-current-limit threshold, and the current-sense
resistor.
the controller responds with a greater duty cycle. The
response time (t RESPONSE ) depends on the closed-loop
bandwidth of the converter. The resistive drop across
the capacitor ESR and capacitor discharge causes a
I REVERSE =
2 × V CLR
R SENSE
(24)
voltage drop during a step load. Use a combination of
SP polymer and ceramic capacitors for better transient
load and ripple/noise performance.
Keep the maximum output voltage deviation less than
or equal to the adaptive voltage-positioning window
( ? V OUT ). Assume 50% contribution each from the out-
put capacitance discharge and the ESR drop. Use the
following equations to calculate the required ESR and
capacitance value:
where I REVERSE is the total reverse current into the con-
verter.
Compensation
The main control loop consists of an inner current loop
and an outer voltage loop. The MAX5065/MAX5067 use
an average-current-mode control scheme to regulate
the output voltage (Figure 4). I PHASE1 and I PHASE2 are
the inner average current loops. The VEA output pro-
vides the controlling voltage for these current sources.
ESR OUT =
? V ESR
I STEP
(20)
The inner current loop absorbs the inductor pole reduc-
ing the order of the outer voltage loop to that of a sin-
gle-pole system.
C OUT = STEP RESPONSE
I × t
? V Q
(21)
A resistive feedback around the VEA provides the best
possible response, since there are no capacitors to
charge and discharge during large-signal excursions, R F
and R IN determine the VEA gain. Use the following equa-
where I STEP is the load step and t RESPONSE is the
tion to calculate the value for R F :
response time of the controller. Controller response
time depends on the control-loop bandwidth.
Current Limit
R F =
I OUT × R IN
N × G C × ? V OUT
(25)
The average-current-mode control technique of the
MAX5065/MAX5067 accurately limits the maximum out-
put current per phase. The MAX5065/MAX5067 sense
the voltage across the sense resistor and limit the peak
G C =
0.05
R S
(26)
R SENSE =
I OUT
2 . 5 × 10 ? 3
PD R =
2 × f SW × L × 10 2 (27)
R CF ≤
inductor current (I L-PK ) accordingly. The ON cycle ter-
minates when the current-sense voltage reaches 45mV
(min). Use the following equation to calculate maximum
current-sense resistor value:
0.045
(22)
N
(23)
R SENSE
where PD R is the power dissipation in sense resistors.
Select 5% lower value of R SENSE to compensate for any
parasitics associated with the PC board. Also, select a
non inductive resistor with the appropriate wattage rating.
Reverse Current Limit
The MAX5065/MAX5067 limit the reverse current when
V BUS is higher than the preset output voltage.
where G C is the current-loop transconductance and N
is number of phases.
When designing the current-control loop ensure that the
inductor downslope (when it becomes an upslope at the
CEA output) does not exceed the ramp slope. This is a
necessary condition to avoid sub-harmonic oscillations
similar to those in peak current-mode control with insuffi-
cient slope compensation. Use the following equation to
calculate the resistor R CF :
V OUT × R SENSE
For example, the maximum R CF is 12k ? for R SENSE =
1.35m ? .
C CF provides a low-frequency pole while R CF provides a
midband zero. Place a zero at f Z to obtain a phase bump
at the crossover frequency. Place a high-frequency pole
28
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