参数资料
型号: MAX5176BEEE+
厂商: Maxim Integrated Products
文件页数: 16/16页
文件大小: 0K
描述: IC DAC 12BIT LP SERIAL 16-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 100
设置时间: 18µs
位数: 12
数据接口: 串行
转换器数目: 1
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-QSOP
包装: 管件
输出数目和类型: 1 电压,单极;1 电压,双极
采样率(每秒): *
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
_______________________________________________________________________________________
9
Typical Operating Characteristics (continued)
(MAX5174: VDD = +5V, VREF = 2.5V; MAX5176: VDD = +3V, VREF = +1.25V; CL = 100pF, OS = AGND, code = FFF hex,
TA = +25°C, unless otherwise noted.)
SCLK
2V/div
OUT
500
V/div
2
s/div
DIGITAL FEEDTHROUGH (SCLK, OUT)
MAX5174/6 toc26
AC-COUPLED
-30
-15
-20
-25
-5
-10
0
5
0
1000
1500
500
2000
2500
3000
REFERENCE INPUT
FREQUENCY RESPONSE
MAX5174/6toc27
FREQUENCY (kHz)
GAIN
(dB)
VREF = 0.67Vp-p + 0.75VDC
50ms/div
START-UP GLITCH
VOUT
10mV/div
AC-COUPLED
MAX5174/6 toc28
VDD
1V/div
MAX5176
Pin Description
Voltage Output. High impedance when in shutdown. The output voltage is limited to VDD.
OUT
2
Power-Down Lockout. (digital input). Connect to VDD to allow shutdown. Connect to DGND to disable
software and hardware shutdown.
PDL
4
Reset Mode Select (digital input). Connect to VDD to select midscale reset output voltage. Connect to
DGND to select 0 reset output voltage.
RS
3
Chip-Select Input (digital input). DIN ignored when CS is high.
CS
6
Serial Clock Input (digital input).
SCLK
8
Serial-Data Input (digital input). Data is clocked in on the rising edge of SCLK.
DIN
7
Clear DAC. (digital input) Clears the DAC to either zero or midscale as determined by RS.
CLR
5
Serial-Data Output
DOUT
10
Shutdown (digital input). Pulling SHDN high when PDL = VDD places the chip in shutdown with a maximum
shutdown current of 10A.
SHDN
12
User-Programmable Output. State is set by the serial input.
UPO
11
Reference Input. Maximum VREF is VDD - 1.4V.
REF
14
PIN
Positive Supply. Bypass to AGND with a 4.7F capacitor in parallel with a 0.1F capacitor.
VDD
16
Offset Adjustment. Connect to AGND for no offset.
OS
1
FUNCTION
NAME
No Connection
N.C.
15
Analog Ground
AGND
13
Digital Ground
DGND
9
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