参数资料
型号: MAX5176BEEE+
厂商: Maxim Integrated Products
文件页数: 4/16页
文件大小: 0K
描述: IC DAC 12BIT LP SERIAL 16-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 100
设置时间: 18µs
位数: 12
数据接口: 串行
转换器数目: 1
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-QSOP
包装: 管件
输出数目和类型: 1 电压,单极;1 电压,双极
采样率(每秒): *
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
12
______________________________________________________________________________________
User-Programmable Logic Output (UPO)
The user-programmable logic output (UPO) allows con-
trol of an external device through the serial interface,
thereby reducing the number of microcontroller I/O pins
required. During power-down, this output will retain its
digital state prior to shutdown. When CLR is pulled low,
UPO will reset to its programmed default state. See
Table 1 for specific commands to control the UPO.
Reset (RS) and Clear (
CLR)
The MAX5174/MAX5176 offers a clear pin (CLR), which
resets the output voltage. If RS = DGND, then CLR
resets the output voltage to 0. If RS = VDD, then CLR
resets the output voltage to mid-scale. In either case,
CLR will reset UPO to its programmed default state.
Applications Information
Unipolar Output
Figure 6 shows the MAX5174/MAX5176 configured for
unipolar, rail-to-rail operation with a gain of 1.638V/V.
Table 2 lists the codes for unipolar output voltages. The
output voltage is limited to VDD. Use the OS pin to intro-
duce an offset voltage as shown in Figure 7 and
described in the
Offset and Buffer Configurations section.
Bipolar Output
Figure 8 shows the MAX5174/MAX5176 configured for
bipolar output operation. The output voltage is given by
the following equation (OS = AGND):
where N represents the numeric value of the DAC’s
binary input code and VREF is the voltage of the exter-
nal reference. Table 3 shows digital codes and the cor-
responding output voltage for Figure 8’s circuit.
VV
N
OUT
REF
=
2
4096
1
CS
SCLK
DIN
COMMAND
EXECUTED
9
8
16
1
C1
C2
S0
C0
D9
D8
D7
D6
D3
D2
D1
D0
S2
S1
D5
D4
Figure 4. Serial-Interface Timing Diagram
CS
SCLK
DIN
DOUT
tCSW
tCS1
tCSH
tCSS
tCSO
tD02
tCH
tCL
tCP
tD01
tDS
tDH
Figure 5. Detailed Serial-Interface Timing Diagram
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