参数资料
型号: MAX5176BEEE+
厂商: Maxim Integrated Products
文件页数: 5/16页
文件大小: 0K
描述: IC DAC 12BIT LP SERIAL 16-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 100
设置时间: 18µs
位数: 12
数据接口: 串行
转换器数目: 1
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-QSOP
包装: 管件
输出数目和类型: 1 电压,单极;1 电压,双极
采样率(每秒): *
MAX5174/MAX5176
Low-Power, Serial, 12-Bit DACs
with Voltage Output
Offset and Buffer Configurations
The simple circuit of Figure 7 illustrates how to intro-
duce an offset to the output voltage. The amount of off-
set introduced by a voltage at the OS pin is shown in
the following equation:
VOFFSET = VOS (1- Gain)
where Gain = 1.638.
However, the total output voltage of the device cannot
exceed VDD, regardless of the voltage on the OS pin.
To set the gain of the output amplifier to 1, connect OS
to OUT.
Daisy-Chaining Devices
The serial-data output pin (DOUT) allows multiple
MAX5174/MAX5176s to be daisy-chained together as
shown in Figure 9. The advantage of this is that only two
lines are needed to control all the DACs. The disadvan-
tage is that it takes
n commands to program the DACs.
Figure 10 shows several MAX5174/MAX5176s sharing
one common DIN signal line. In this configuration the
data bus is common to all devices; however, more I/O
lines are required because each device needs a dedi-
cated CS line. The advantage of this configuration is
that only one command is needed to program any DAC.
DAC CONTENTS
MSB
LSB
11 1111 1111 11 (00)
10 0000 0000 01 (00)
+VREF (2049/4096) 1.638
+VREF (4095/4096) 1.638
ANALOG OUTPUT
10 0000 0000 00 (00)
+VREF (2048/4096) 1.638
01 1111 1111 11 (00)
+VREF (2047/4096) 1.638
00 0000 0000 01 (00)
+VREF (1/4096) 1.638
00 0000 0000 00 (00)
0
Table 2. Unipolar Code Table
(Circuit of Figure 6)
MAX5174
MAX5176
DAC
REF
OUT
OS
DGND
AGND
+5V/+3V
VDD
Figure 6. Unipolar Output Circuit (Rail-to-Rail)
DAC CONTENTS
MSB
LSB
11 1111 1111 11 (00)
10 0000 0000 01 (00)
+VREF [(2 2049/4096) - 1]
+VREF [(2 4095/4096) - 1]
ANALOG OUTPUT
01 1111 1111 11 (00)
+VREF [(2 2047/4096) - 1]
00 0000 0000 01 (00)
+VREF [(2 1/4096) - 1]
10 0000 0000 00 (00)
+VREF [(2 2048/4096) - 1]
00 0000 0000 00 00
-VREF
Table 3. Bipolar Code Table
(Circuit of Figure 8)
Figure 7. Setting OS for Output Offset
MAX5174
MAX5176
DAC
AGND
DGND
REF
OUT
OS
VOS
+5V/+3V
VDD
________________________________________________________________________________________13
TOLERANCES: 10k
±0.1%
AGND
DGND
MAX5174
MAX5176
DAC
REF
OS
OUT
10k
V-
V+
VDD
VOUT
+5V/+3V
Figure 8. Bipolar Output Circuit
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