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参数资料
| 型号： | MAX5858ECM+TD |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 19/23页 |
| 文件大小： | 0K |
| 描述： | IC DAC 10BIT DUAL 300MSPS 48TQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,000 |
| 设置时间： | 11ns |
| 位数： | 10 |
| 数据接口： | 并联 |
| 转换器数目： | 2 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 816mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TQFP 裸露焊盘 |
| 供应商设备封装： | 48-TQFP 裸露焊盘（7x7） |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 2 电流，单极 |
| 采样率（每秒）： | 300M |
MAX5858
Dual, 10-Bit, 300Msps, Current-Output DAC with
4x/2x/1x Interpolation Filters
_______________________________________________________________________________________
5
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, no interpolation, external reference, VREF = 1.2V,
IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA > +25°C guaranteed by
production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DATA-to-CLK Rise Setup Time
tDCSR
(Note 3)
1.5
ns
DATA-to-CLK Rise Hold Time
tDCHR
(Note 3)
0.4
ns
DATA-to-CLK Fall Setup Time
tDCSF
(Note 3)
1.7
ns
DATA-to-CLK Fall Hold Time
tDCHF
(Note 3)
1.1
ns
Control Word to
CW Fall Setup
Time
tCWS
2.5
ns
Control Word to
CW Fall Hold
Time
tCWH
2.5
ns
CW High Time
5ns
CW Low Time
5ns
DACEN Rise-to-VOUT Stable
tSTB
0.7
s
PD Fall-to-VOUT Stable
tPDSTB
External reference
0.5
ms
Clock Frequency at
CLKXP/CLKXN Input
fDAC
Differential clock
300
MHz
CLKXP/CLKXN Differential Clock
Input to CLK Output Delay
tCXD
4.6
ns
Minimum CLKXP/CLKXN Clock
High Time
tCXH
1.5
ns
Minimum CLKXP/CLKXN Clock
Low Time
tCXL
1.5
ns
POWER REQUIREMENTS
Analog Power-Supply Voltage
AVDD
2.7
3.3
V
Analog Supply Current
IAVDD
(Note 4)
45
49
mA
Digital Power-Supply Voltage
DVDD
2.7
3.3
V
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