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参数资料
| 型号： | MAX5887EGK+D |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 2/18页 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT 3.3V 500MSPS 68-QFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 30 |
| 设置时间： | 11ns |
| 位数： | 14 |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 130mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 68-VFQFN 裸露焊盘 |
| 供应商设备封装： | 68-QFN 裸露焊盘（10x10） |
| 包装： | 管件 |
| 输出数目和类型： | 2 电流，单极 |
| 采样率（每秒）： | 500M |
MAX5887
3.3V, 14-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
10
______________________________________________________________________________________
plane, IOUTP should be selected as the output, with
IOUTN connected to AGND. Note that a single-ended
output configuration has a higher 2nd-order harmonic
distortion at high output frequencies than a differential
output configuration.
Figure 3 displays a simplified diagram of the internal
output structure of the MAX5887.
Clock Inputs (CLKP, CLKN)
The MAX5887 features a flexible differential clock input
(CLKP, CLKN) operating from separate supplies
(VCLK, CLKGND) to achieve the lowest possible jitter
performance. The two clock inputs can be driven from
a single-ended or a differential clock source. For sin-
gle-ended operation, CLKP should be driven by a logic
source, while CLKN should be bypassed to AGND with
a 0.1F capacitor.
The CLKP and CLKN pins are internally biased to 1.5V.
This allows the user to AC-couple clock sources directly
to the device without external resistors to define the DC
level. The input resistance of CLKP and CLKN is >5k
.
See Figure 4 for a convenient and quick way to apply a
differential signal created from a single-ended source
(e.g., HP 8662A signal generator) and a wideband
transformer. These inputs can also be driven from an
LVDS-compatible clock source; however, it is recom-
mended to use sinewave or AC-coupled ECL drive for
best performance.
Data Timing Relationship
Figure 5 shows the timing relationship between differ-
ential, digital LVDS data, clock, and output signals. The
MAX5887 features a 1.8ns hold, a -0.8ns setup, and a
1.8ns propagation delay time. There is a 3.5 clock-
cycle latency between CLKP/CLKN transitioning
high/low and IOUTP/IOUTN.
LVDS-Compatible Digital Inputs
(B0P–B13P, B0N–B13N)
The MAX5887 features LVDS receivers on the bus input
interface. These LVDS inputs (B0P/N through B13P/N)
allow for a low-differential voltage swing with low con-
stant power consumption across a large range of
0.1
F
1.2V
REFERENCE
10k
IREF
RSET
DACREF
FSADJ
REFIO
IREF = VREFIO/RSET
CURRENT-STEERING
DAC
AVDD
IOUTP
IOUTN
Figure 2. Reference Architecture, Internal Reference
Configuration
IOUT
IOUTN
IOUTP
CURRENT
SOURCES
CURRENT
SWITCHES
AVDD
Figure 3. Simplified Analog Output Structure
SINGLE-ENDED
CLOCK SOURCE
(e.g., HP 8662A)
1:1
WIDEBAND RF TRANSFORMER
PERFORMS SINGLE-ENDED TO
DIFFERENTIAL CONVERSION.
TO
DAC
CLKP
0.1
F
0.1
F
CLKN
CLKGND
25
25
Figure 4. Differential Clock Signal Generation
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX5887EGK-TD | 功能描述:数模转换器- DAC RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| MAX5887EVKIT | 功能描述:数模转换器- DAC Evaluation Kit for the MAX5886 MAX5887 MAX5888 RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| MAX5888AEGK | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MAX5888AEGK+D | 功能描述:数模转换器- DAC 16-Bit 500Msps DAC RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| MAX5888AEGK+TD | 功能描述:数模转换器- DAC 16-Bit 500Msps DAC RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
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