参数资料
型号: MAX5975BETE+T
厂商: Maxim Integrated Products
文件页数: 15/20页
文件大小: 0K
描述: IC REG CTRLR FLYBK ISO CM 16TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 电流模式
输出数: 1
频率 - 最大: 600kHz
占空比: 84%
电源电压: 12 V ~ 24 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 16-WFQFN 裸露焊盘
包装: 带卷 (TR)
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
Frequency Foldback for High-Efficiency
Light-Load Operation
The frequency foldback threshold can be programmed
from 0 to 20% of the full load current using a resistor from
FFB to GND.
Figure 4 shows device operation in frequency foldback
mode. Calculate the value of R FFB as follows:
where R SS is the resistor connected between SS and
GND, and I SS-CH is the current sourced from SS to R SS
(10 F A typ).
DCLMP
To set D MAX using supply voltage feed forward, connect
a resistive divider between the supply voltage, DCLMP,
and GND as shown in the Typical Applications Circuits.
R FFB =
10 × I LOAD(LIGHT) × R CS
I FFB
This feed-forward duty-cycle clamp ensures that the
external n-channel MOSFET is not stressed during sup-
ply transients. V DCLMP is calculated as follows:
V DCLMP =
× V S
whereR FFB istheresistorconnectedtoFFB,I LOAD(LIGHT)
is the current at light-load conditions that triggers fre-
quency foldback, R CS is the value of the sense resistor
connected between CS and PGND, and I FFB is the cur-
rent sourced from FFB to R FFB (30 F A typ).
Duty-Cycle Clamping
The maximum duty cycle is determined by the lowest
of three voltages: 2V, the voltage at SS (V SS ), and the
voltage (2.43V - V DCLMP ). The maximum duty cycle is
calculated as:
R DCLMP2
R DCLMP1 + R DCLMP2
where R DCLMP1 and R DCLMP2 are the resistive divider
values shown in the Typical Applications Circuits and V S
is the input supply voltage.
Oscillator Synchronization
The internal oscillator can be synchronized to an exter-
nal clock by applying the clock to SYNC/DITHER direct-
ly. The external clock frequency can be set anywhere
D MAX =
V MIN
2.43V
between 1.1x to 2x the internal clock frequency.
Using an external clock increases the maximum duty
where V MIN = minimum (2V, V SS , 2.43V - V DCLMP ).
SS
By connecting a resistor between SS and ground, the
voltage at SS can be made to be lower than 2V. V SS is
calculated as follows:
cycle by a factor equal to f SYNC /f SW . This factor should
be accounted for in setting the maximum duty cycle
using any of the methods described in the Duty-Cycle
Clamping section. The formula below shows how the
maximum duty cycle is affected by the external clock
frequency:
× SYNC
V CSAVG
FFB
NDRV
V SS = R SS × I SS ? CH
D MAX =
V MIN f
2.43V f SW
t SW
t SW X 2
t SW X 2
COMP
Figure 4. Entering Frequency Foldback
15
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