参数资料
型号: MAX5975BETE+T
厂商: Maxim Integrated Products
文件页数: 17/20页
文件大小: 0K
描述: IC REG CTRLR FLYBK ISO CM 16TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 电流模式
输出数: 1
频率 - 最大: 600kHz
占空比: 84%
电源电压: 12 V ~ 24 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 16-WFQFN 裸露焊盘
包装: 带卷 (TR)
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
MAX5975A
Typically, offline power supplies keep startup times to
less than 500ms even in low-line conditions (85V AC
input for universal offline or 36V DC for telecom applica-
tions). Size the startup resistor, R IN , to supply both the
maximum startup bias of the device (150 F A) and the
charging current for C IN . C IN must be charged to 20V
within the desired 500ms time period. C IN must store
enough charge to deliver current to the device for at
least the soft-start time (t SS ) set by C SS . To calculate the
approximate amount of capacitance required, use the
MAX5975B
The parameters governing the design of the bootstrap
circuit are different for the MAX5975B. While the above
design equations remain valid, the following values must
be used when designing for R IN and C IN : V HYST = 3V and
V S(MIN) is the minimum output voltage of the wall adapter.
Bias Circuit
An in-phase tertiary winding is needed to power the bias
circuit. The voltage across the tertiary V T during the on-
time is:
C IN = IN G SS
V T = V OUT × T
N
following formula:
I G = Q GTOT f SW
(I + I )(t  )
V HYST
N
S
where V OUT is the output voltage and N T /N S is the turns
ratio from the tertiary to the secondary winding. Select the
where I IN is the internal supply current (1.7mA) after
startup, Q GTOT is the total gate charge for the n-channel
FET, f SW is the switching frequency, V HYST is the boot-
strap UVLO hysteresis (13V typ), and t SS is the soft-start
time. R IN is then calculated as follows:
turns ratio so that V T is above the UVLO shutdown level
(7.5V max).
Layout Recommendations
Typically, there are two sources of noise emission in a
switching power supply: high di/dt loops and high dV/dt
surfaces. For example, traces that carry the drain current
R IN ?
V S(MIN) ? V INUVR
I START
often form high di/dt loops. Similarly, the heatsink of the
main MOSFET presents a dV/dt source; therefore, mini-
mize the surface area of the MOSFET heatsink as much
where V S(MIN) is the minimum input supply voltage for
the application (36V for telecom), V INUVR is the boot-
strap UVLO wake-up level (20V), and I START is the IN
supply current at startup (150 F A max).
Choose a higher value for R IN than the one calculated
above if longer startup time can be tolerated in order to
as possible. Keep all PCB traces carrying switching cur-
rents as short as possible to minimize current loops. Use
a ground plane for best results.
For universal AC input design, follow all applicable
safety regulations. Offline power supplies may require
UL, VDE, and other similar agency approvals.
minimize power loss on this resistor.
17
相关PDF资料
PDF描述
H2BBG-10103-Y4-ND JUMPER-H1501TR/A2015Y/H1501TR 3"
VI-24H-EW-F2 CONVERTER MOD DC/DC 52V 100W
VI-24F-EY-B1 CONVERTER MOD DC/DC 72V 50W
MAX5974AETE+T IC REG CTRLR FLYBACK PWM 16-TQFN
H2BBG-10103-W4-ND JUMPER-H1501TR/A2015W/H1501TR 3"
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