参数资料
型号: MAX6874ETJ+
厂商: Maxim Integrated Products
文件页数: 16/40页
文件大小: 0K
描述: IC SEQUENCE/SUPERVISOR 32TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 43
类型: 序列发生器
监视电压数目: 6
输出: 开路漏极,推挽式
复位: 高有效/低有效
复位超时: 可调节/可选择
电压 - 阀值: 8 种可选阀值组合
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x5)
包装: 管件
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
Table 7. PO1 (MAX6874 Only) Output Dependency
REGISTER
ADDRESS
0Eh
0Fh
10h
11h
40h
EEPROM
MEMORY
ADDRESS
800Eh
800Fh
8010h
8011h
8040h
BIT
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[5:0]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[0]
OUTPUT ASSERTION CONDITIONS
1 = PO1 assertion depends on IN1 undervoltage threshold (Table 2).
1 = PO1 assertion depends on IN2 undervoltage threshold (Table 3).
1 = PO1 assertion depends on IN3 undervoltage threshold (Table 4).
1 = PO1 assertion depends on IN4 undervoltage threshold (Table 4).
1 = PO1 assertion depends on IN5 undervoltage threshold (Table 4).
1 = PO1 assertion depends on IN6 undervoltage threshold (Table 4).
1 = PO1 assertion depends on watchdog (Tables 19 and 20).
Must be set to 0.
Must be set to 0.
1 = PO1 assertion depends on GPI1 (Table 5).
1 = PO1 assertion depends on GPI2 (Table 5).
1 = PO1 assertion depends on GPI3 (Table 5).
1 = PO1 assertion depends on GPI4 (Table 5).
1 = PO1 assertion depends on PO2 (Table 8).
1 = PO1 assertion depends on PO3 (Table 9).
1 = PO1 assertion depends on PO4 (Table 10).
1 = PO1 assertion depends on PO5 (Table 11).
1 = PO1 assertion depends on PO6 (Table 12).
1 = PO1 assertion depends on PO7 (Table 13).
1 = PO1 assertion depends on PO8 (Table 14).
1 = PO1 asserts when MR = low (Table 6).
on no condition always remains in its active state (Table
19). An output configured as active-high is considered
asserted when that output is logic high. No output can
depend solely on MR .
The voltage monitors generate fault signals (logical 0) to
the MAX6874/MAX6875s’ logic array when an input volt-
age is below the programmed undervoltage threshold.
Registers 0Eh through 3Ah and 40h configure each of the
programmable outputs. Programmable timing blocks set
the PO_ timeout period from 25μs to 1600ms for each
programmable output. See register 3Ah (Table 15) to set
the active state (active-high or active-low) for each pro-
grammable output and Table 16 for timeout periods for
each output.
For example, PO3 (MAX6874—Table 9) may depend on
the IN1 undervoltage threshold, and the states of GPI1,
PO1, and PO2. Write a one to R16h[0], R17h[6], and
R18h[3:2] to configure the output as indicated. IN1 must
be above the undervoltage threshold (Table 2), GPI1
must be inactive (Table 5), and PO1 (Tables 7 and 15)
and PO2 (Table 9) must be in their deasserted states for
the output to deassert.
Table 7 only applies to PO1 of the MAX6874. Write a 0
to a bit to make the PO1 output independent of the
respective signal (IN1–IN6 thresholds, WD, GPI1–GPI4,
MR , or other programmable outputs).
16
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