参数资料
型号: MAX6898PALT+T
厂商: Maxim Integrated Products
文件页数: 7/15页
文件大小: 0K
描述: IC SEQUENCE/SUPERVISOR 6UDFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
类型: 序列发生器
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 可调节/可选择
电压 - 阀值: 可调节/可选择
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 6-WFDFN
供应商设备封装: 6-uDFN(1.5x1.0)
包装: 标准包装
其它名称: MAX6898PALT+TDKR
MAX6895–MAX6899
Ultra-Small, Adjustable
Sequencing/Supervisory Circuits
Monitor Input (IN)
Connect the center point of a resistive divider to IN to
monitor external voltages (see R1 and R2 of the Typical
Operating Circuit). IN has a rising threshold of V TH =
0.5V and a falling threshold of 0.495V (5mV hysteresis).
When V IN rises above V TH and ENABLE is high (or
ENABLE is low) OUT goes high ( OUT goes low) after
the programmed t DELAY period. When V IN falls below
0.495V, OUT goes low ( OUT goes high) after a 16μs
delay. IN has a maximum input current of 15nA so
large-value resistors are permitted without adding sig-
nificant error to the resistive divider.
Adjustable Delay (CDELAY)
When V IN rises above V TH with ENABLE high ( ENABLE
low), the internal 250nA current source begins charging
an external capacitor connected from CDELAY to GND.
When the voltage at CDELAY reaches 1V, the output
V CC
V UVLO
asserts (OUT goes high or OUT goes low). When the
output asserts, C CDELAY is immediately discharged.
Adjust the delay (t DELAY ) from when V IN rises above
V TH (with ENABLE high or ENABLE low) to OUT going
high ( OUT going low) according to the equation:
t DELAY = C CDELAY x 4.0 x 10 6 + 40μs
where C CDELAY is the external capacitor from CDELAY
to GND.
For adjustable delay devices (A version), when V IN >
0.5V and ENABLE goes from low to high ( ENABLE
goes from high to low) the output asserts after a t DELAY
period. For nonadjustable delay devices (P version)
there is a 1μs propagation delay from when the enable
input is asserted to when the output asserts. Figures 2
through 5 show the timing diagrams for the adjustable
and fixed delay versions, respectively.
IN
V TH
V TH
t < t PROPA
ENABLE
t > t PW
OUT
t PROPA
Figure 2. MAX6895A/MAX6897A Timing Diagram
Maxim Integrated
t DL
t DELAY
t OFF
t PROPA
7
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